diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-08-19 11:43:29 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-11 15:15:54 +0000 |
| commit | abbb5b58ec191ac73b4cbfd5ce5a5bd529958cf9 (patch) | |
| tree | 7753969557118975e18ae547ed3f21f47a941472 /src/mainboard | |
| parent | 3df6f4192835d1a15c2d08a74de9b1ce05528b65 (diff) | |
mb/google/guybrush: Use register and bit defines for eSPI setup
It's hard to understand what this code is doing because it uses hard
coded values, so use the register and bit defines instead.
BUG=none
TEST=Timeless build for guybrush results in identical binary.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 28 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/verstage.c | 13 |
2 files changed, 23 insertions, 18 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index cd27632498..5857d85b1b 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -2,12 +2,15 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/lpc.h> #include <bootblock_common.h> #include <baseboard/variants.h> #include <console/console.h> #include <delay.h> #include <device/pci_ops.h> +#include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/southbridge.h> #include <timer.h> #define FC350_PCIE_INIT_DELAY_US (20 * USECS_PER_MSEC) @@ -31,12 +34,13 @@ void bootblock_mainboard_early_init(void) size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - dword = pci_read_config32(SOC_LPC_DEV, 0x78); - dword &= 0xFFFFF9F3; - dword |= 0x200; - pci_write_config32(SOC_LPC_DEV, 0x78, dword); - pci_write_config32(SOC_LPC_DEV, 0x44, 0); - pci_write_config32(SOC_LPC_DEV, 0x48, 0); + dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ0_PD_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); + pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0); if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return; @@ -53,13 +57,13 @@ void bootblock_mainboard_early_init(void) stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); - dword = pm_read32(0x90); - dword |= 1 << 16; - pm_write32(0x90, dword); + dword = pm_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_read32(0x74); - dword |= 3 << 10; - pm_write32(0x74, dword); + dword = pm_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_write32(PM_ACPI_CONF, dword); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index aaaaf038de..a8c162f59b 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -5,6 +5,7 @@ #include <arch/io.h> #include <baseboard/variants.h> #include <security/vboot/vboot_common.h> +#include <soc/southbridge.h> static void setup_gpio(void) { @@ -29,12 +30,12 @@ void verstage_mainboard_early_init(void) if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { uint32_t dword; printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(0x90); - dword |= 1 << 16; - pm_io_write32(0x90, dword); + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_io_read32(0x74); - dword |= 3 << 10; - pm_io_write32(0x74, dword); + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); } } |