diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 20:08:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-14 11:30:21 +0000 |
| commit | aa990e928910e35edb115095898c4668becdf1d8 (patch) | |
| tree | f7e0baf573f4981b09b823dc884bb16bd9f32b63 /src/mainboard | |
| parent | 399b6c11efaff64cb86a879dc9047a97538e790f (diff) | |
sb/intel/i82801jx: Move early sb init to a common place
Setting southbridge GPIO is now done after console init,
which should be fine. This code is partially copied from
i82801ix.
Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asus/p5qc/romstage.c | 18 | ||||
| -rw-r--r-- | src/mainboard/asus/p5ql-em/romstage.c | 16 | ||||
| -rw-r--r-- | src/mainboard/intel/dg43gt/romstage.c | 18 |
3 files changed, 7 insertions, 45 deletions
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 3462a3d99d..9a90f74189 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -17,7 +17,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -31,20 +30,8 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_misc_rcba(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Set default GPIOs on superio: TODO (here or in ramstage) */ - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; @@ -59,13 +46,14 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); + mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index 142ee73e49..c7ade1c541 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -16,7 +16,6 @@ #include <device/pnp_ops.h> #include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/msr.h> @@ -104,19 +103,6 @@ static int setup_sio_gpio(void) return need_reset; } -static void mb_gpio_init(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); -} - void mainboard_romstage_entry(void) { /* This board has first dimm slot of each channel hooked up to @@ -129,13 +115,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 6e645b5630..b851f98627 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -17,7 +17,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -31,20 +30,8 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_misc_rcba(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Set default GPIOs on superio: TODO (here or in ramstage) */ - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; RCBA32(0x3418) = 0x01320001; @@ -61,13 +48,14 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); + mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); |