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authorFrank Chu <Frank_Chu@pegatron.corp-partner.google.com>2022-11-18 16:28:31 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-11-24 15:15:03 +0000
commita9921bcadb7e8c179c656b7b115bce37cb45f0eb (patch)
tree9cd9283c6e636362dd290c94f3edff27ad746771 /src/mainboard
parent98b696703e8e508dd57b467a557f9bc7567f7e6d (diff)
mb/google/brya/var/marasov: update pch_espi setting
Add conn0/conn1 for pch_espi. BUG=b:254365935 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/variants/marasov/overridetree.cb9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index cb7733580d..70787c611b 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -184,6 +184,13 @@ chip soc/intel/alderlake
device spi 0 on end
end # FPMCU
end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
@@ -195,7 +202,7 @@ chip soc/intel/alderlake
chip drivers/intel/pmc_mux/conn
use usb2_port3 as usb2_port
use tcss_usb3_port3 as usb3_port
- device generic 2 alias conn2 on end
+ device generic 1 alias conn1 on end
end
end
end