diff options
| author | Reka Norman <rekanorman@google.com> | 2022-03-04 13:18:50 +1100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-08 15:01:24 +0000 |
| commit | a909c7f613d8fcb055c6dd38222436be868446ba (patch) | |
| tree | 53c00cb16705d3df459a0e53ca6d0c1c0abd8979 /src/mainboard | |
| parent | 8565b94a5396f8112a9b86c1c7529217dd603c17 (diff) | |
mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe WLAN.
BUG=b:222595137
TEST=Bluetooth works on nivviks
Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Diffstat (limited to 'src/mainboard')
3 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 91c633a3fa..d85e230e5d 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/alderlake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index add5e213f4..9cb27e88d7 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -13,6 +13,7 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN device domain 0 on device ref i2c1 on diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 194b26fa3e..8ccbac7156 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + device domain 0 on device ref ipu on chip drivers/intel/mipi_camera @@ -300,7 +302,7 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port8 on end + device ref usb2_port10 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" |