diff options
| author | Sudheer Kumar Amrabadi <samrabad@codeaurora.org> | 2022-09-16 12:09:19 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-11-07 18:06:36 +0000 |
| commit | 9620ddc8f2095233c1eb6a2c5d2129cd313db4cf (patch) | |
| tree | bb0f445bc2fe2033fccd4de44a0a67f0a55fec05 /src/mainboard | |
| parent | 06d5b8b7fea9e08f3914e6c67592d0f305c8a181 (diff) | |
soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.
BUG=b:218406702
TEST=reboot from AP console (on CRD3)
prior to fix (from cbmem dump):
1000:depthcharge start 1,139,809 (152,679)
after fix (from cbmem dump):
1000:depthcharge start 1,041,109 (46,353)
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/herobrine/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 24d0e28c67..43b72dec5e 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/aop_common.h> #include <soc/cpucp.h> #include <soc/qclib_common.h> #include <soc/shrm.h> @@ -25,6 +26,7 @@ void platform_romstage_main(void) cpucp_prepare(); /* QCLib: DDR init & train */ qclib_load_and_run(); + aop_fw_load_reset(); prepare_usb(); /* This rail needs to be stable by the time we take the FPMCU out of reset in ramstage, so already turn it on here. This needs to happen |