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authorShaunak Saha <shaunak.saha@intel.com>2021-02-17 23:26:43 -0800
committerFurquan Shaikh <furquan@google.com>2021-04-06 23:28:17 +0000
commit82d5123e1ca932b4fcb3117c859027f84873bd70 (patch)
treed8e5a3cd4bf66c4f4f9b7929aa2b2e0d9ebcb78d /src/mainboard
parent967753f0d89274b73665f7aafa06ef2d0eb168ab (diff)
intel/tigerlake: Add Acoustic features
On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb5
-rw-r--r--src/mainboard/google/volteer/variants/delbin/overridetree.cb11
-rw-r--r--src/mainboard/google/volteer/variants/drobit/overridetree.cb11
-rw-r--r--src/mainboard/google/volteer/variants/volteer/overridetree.cb11
-rw-r--r--src/mainboard/google/volteer/variants/volteer2/overridetree.cb11
-rw-r--r--src/mainboard/google/volteer/variants/voxel/overridetree.cb11
6 files changed, 5 insertions, 55 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 5f058446c6..58d1aac79b 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -352,6 +352,11 @@ chip soc/intel/tigerlake
.vnn_sx_voltage_mv = 1250,
}"
+ # Acoustic settings
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRate" = "SLEW_FAST_8"
+ register "FastPkgCRampDisable" = "1"
+
device domain 0 on
device ref igpu on end
device ref dptf on
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb
index c111731387..1549aafe47 100644
--- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb
@@ -57,17 +57,6 @@ chip soc/intel/tigerlake
}"
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
- # Acoustic settings
- register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
- register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
-
register "tcc_offset" = "8"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
index a29ce1c24b..87c1417261 100644
--- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
@@ -2,17 +2,6 @@ chip soc/intel/tigerlake
register "DdiPort1Hpd" = "0"
register "DdiPort2Hpd" = "0"
- # Acoustic settings
- register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
- register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
-
register "tcc_offset" = "8"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
index 10e199ae4d..bce953b8cd 100644
--- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
@@ -49,17 +49,6 @@ chip soc/intel/tigerlake
register "HybridStorageMode" = "1"
- # Acoustic settings
- register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
- register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
-
device domain 0 on
device ref ipu on end
device ref i2c0 on
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index f517de246c..635a310ea8 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -65,17 +65,6 @@ chip soc/intel/tigerlake
register "HybridStorageMode" = "1"
- # Acoustic settings
- register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
- register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
-
device domain 0 on
device ref dptf on
chip drivers/intel/dptf
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index c1002ef752..a1453f950c 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -19,17 +19,6 @@ chip soc/intel/tigerlake
# Disable SRCCLKREQ1#
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
- # Acoustic settings
- register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
- register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
- register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
- register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
-
device domain 0 on
device ref dptf on
chip drivers/intel/dptf