diff options
| author | Chris.Wang <chris.wang@amd.corp-partner.google.com> | 2023-03-16 15:24:02 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 13:21:01 +0000 |
| commit | 77c5d898aecbb15b37e4458cd32ca95f10e2264e (patch) | |
| tree | cc8dc8e9750672bfde4e0d2a7c9bf9c912d2f50e /src/mainboard | |
| parent | f83b282856ebf83194fd7e2bd7adb5e65a2bd384 (diff) | |
mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms
between backlight on and vary backlight.
BUG=b:271704149
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table;
measure the power on sequence on whiterun
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 0cf9ba588b..4297f903b0 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -112,6 +112,9 @@ chip soc/amd/mendocino register "dxio_tx_vboost_enable" = "1" + # The unit is set to one per 4ms + register "pwr_on_vary_bl_to_blon" = "0x1c" + device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device |