diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-07-29 10:55:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-07 14:27:15 +0000 |
| commit | 778c7af37ae399cfd72178f4585f3ba626ed84cf (patch) | |
| tree | 2772f54f1c11ee702c0184d42ee0dd6af10a5e2a /src/mainboard | |
| parent | 640b040f6f204f39a5f710fa019ab9077674826c (diff) | |
mb/intel/adlrvp: Fix expected statement
Switch cases expect a statement so move the default label.
TEST: With BUILD_TIMELESS=1 binary remains identical.
Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66266
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory_rpl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/memory_rpl.c b/src/mainboard/intel/adlrvp/memory_rpl.c index a541fbf1e2..8302a06d1f 100644 --- a/src/mainboard/intel/adlrvp/memory_rpl.c +++ b/src/mainboard/intel/adlrvp/memory_rpl.c @@ -18,11 +18,11 @@ void rpl_memory_params(FSPM_UPD *memupd) case ADL_P_DDR4_2: case ADL_P_DDR5_1: case ADL_P_DDR5_2: + default: return; case ADL_P_LP5_1: case ADL_P_LP5_2: mem_cfg->Lp5BankMode = 1; return; - default: } } |