diff options
author | Nico Huber <nico.h@gmx.de> | 2024-06-02 02:20:54 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2024-11-21 09:25:47 +0000 |
commit | 755ecc259c42e867566bae96aa0103c15a435aa5 (patch) | |
tree | aabed210fb8e8a91a03c75e2a89c6554cc3085cf /src/mainboard | |
parent | 60f388f9845afdf50eb51f5a06f03cd6d72988b1 (diff) |
nb/via/cx700: Implement raminit
This brings the old raminit implementation for CX700 back. It was
removed in commit e99f0390b9b8 (Remove VIA CX700 northbridge sup-
port). The code is mostly unchanged, three minor issues are fixed:
* A shift (>>= 2) was missing when reading tRRD from SPD byte 28.
The fixed value matches what the vendor BIOS of a VIA EPIA-EX
board programs. The code also suggests that we are looking for
a small value (<= 19 for DDR2-533).
* We allow the board port to specify which clock outputs should
be enabled now. This is necessary for the VIA EPIA-EX, which
needs the ALL_MCLKO setting (instead of the previously hard-
coded MCLKO2.
* When programming the DQS output delays, we considered the 1~2
rank values only for single-rank configurations. Changing the
`< 2` to `<= 2` brings us closer to the vendor values on the
VIA EPIA-EX.
Otherwise a lot of cosmetics changed. Partly because the original
code was to be #included into another C file, but also to satisfy
checkpatch. Also, all the #if'd code was removed (32-bit width
option, ECC, etc.).
Change-Id: Ibc36b4f314cdf47f18c8be0fcb98218c50938e94
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/via/epia-ex/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/via/epia-ex/devicetree.cb b/src/mainboard/via/epia-ex/devicetree.cb index 3f76279175..732d02490c 100644 --- a/src/mainboard/via/epia-ex/devicetree.cb +++ b/src/mainboard/via/epia-ex/devicetree.cb @@ -1,6 +1,14 @@ chip northbridge/via/cx700 device domain 0 on + + device ref dram_ctrl on + register "dram_cfg" = "{ + .spd_addr = { 0x50, }, + .mem_clocks = ALL_MCLKO, + }" + end + end end |