diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-21 07:26:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-22 15:30:50 +0000 |
| commit | 75178071fb852970485b8bfe5a151a153f446792 (patch) | |
| tree | 283de7fb43d19c66e479ed66757e272b8fa201df /src/mainboard | |
| parent | b90aba43c1405d3d2cb7cba05e68906e979dcda3 (diff) | |
mb/siemens/mc_ehl1: Disable power management features for SATA
Features like DevSLP and Aggressive Link Power Management are not
supported on this mainboard and are therefore disabled.
Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 4da94d9734..d08ac368a4 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -64,11 +64,11 @@ chip soc/intel/elkhartlake register "PcieClkSrcClkReq[5]" = "0xFF" # Storage (SATA/SDCARD/EMMC) related UPDs - register "SataSalpSupport" = "1" + register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[1]" = "0" register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcDdr50Enabled" = "1" |