diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-07-20 08:56:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 13:20:40 +0000 |
| commit | 6e0de5d9cc8ba6aefc5407f91a6c00781d19ab8e (patch) | |
| tree | a3e07df368e41dbfb51f04e8da11354d14ae0751 /src/mainboard | |
| parent | ef4f2cd38e5ec4d6282e6e9fa97bad7ec8877743 (diff) | |
mb/ibm/sbp1: Drop SuperIO code
The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.
Add the virtual UART on 0x3f8 as ACPI device.
TEST: Verified on SBP1 that serial still works.
Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/ibm/sbp1/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/ibm/sbp1/acpi/platform.asl | 13 | ||||
| -rw-r--r-- | src/mainboard/ibm/sbp1/bootblock.c | 7 | ||||
| -rw-r--r-- | src/mainboard/ibm/sbp1/devicetree.cb | 9 |
4 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/ibm/sbp1/Kconfig b/src/mainboard/ibm/sbp1/Kconfig index 69974862e5..150c71ca27 100644 --- a/src/mainboard/ibm/sbp1/Kconfig +++ b/src/mainboard/ibm/sbp1/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS select MEMORY_MAPPED_TPM select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP - select SUPERIO_ASPEED_AST2400 # Check if AST2400 is compatible select HAVE_ACPI_TABLES select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/ibm/sbp1/acpi/platform.asl b/src/mainboard/ibm/sbp1/acpi/platform.asl index 7ab8f8e27b..76704fb7b9 100644 --- a/src/mainboard/ibm/sbp1/acpi/platform.asl +++ b/src/mainboard/ibm/sbp1/acpi/platform.asl @@ -21,6 +21,19 @@ Field (DBG0, ByteAcc, Lock, Preserve) IO81, 8 } +/* Virtual UART on 0x3f8 */ +Scope(\_SB) { + Device(COM1) { + Name(_HID, EisaId("PNP0501")) + Name(_UID, 0x01) + Name(_STA,0x0F) + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08) + IRQNoFlags() { 4 } + }) + } +} + /* * The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c index e04d8ef6be..bb18228548 100644 --- a/src/mainboard/ibm/sbp1/bootblock.c +++ b/src/mainboard/ibm/sbp1/bootblock.c @@ -8,24 +8,21 @@ #include <soc/intel/common/block/lpc/lpc_def.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <superio/aspeed/ast2400/ast2400.h> -#include <superio/aspeed/common/aspeed.h> -#define ASPEED_SIO_PORT 0x2E #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 void bootblock_mainboard_early_init(void) { uint16_t lpciod = LPC_IOD_COMA_RANGE; - uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN); + uint16_t lpcioe = LPC_IOE_COMA_EN; /* Open IO windows: 0x3f8 for com1 */ pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); /* LPC I/O enable: com1 */ pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); - /* Enable com1 (0x3f8) and superio (0x2e) */ + /* Enable com1 (0x3f8) */ pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); } diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb index 99c14b17f5..6fee7b88b0 100644 --- a/src/mainboard/ibm/sbp1/devicetree.cb +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -6,15 +6,6 @@ chip soc/intel/xeon_sp/spr device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 device pci 1f.0 on # Intel device 1b81: PCH eSPI controller - chip superio/common - device pnp 2e.0 on - chip superio/aspeed/ast2400 - register "use_espi" = "1" - device pnp 2e.2 off end # SUART1 - device pnp 2e.3 off end # SUART2 - end - end - end chip drivers/ipmi # BMC KCS device pnp ca2.0 on end register "bmc_i2c_address" = "0x20" |