diff options
| author | Caveh Jalali <caveh@google.com> | 2018-01-17 17:40:27 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-25 15:56:20 +0000 |
| commit | 6de0cd2b7d7c6611ac743575032d4163a6759f8c (patch) | |
| tree | c852589a7b79edb7cce605baf223addb5bfb24b0 /src/mainboard | |
| parent | f56e71b4d20bf19a74562f4ea080fe467fc8e088 (diff) | |
mainboard/google/zoombini: add ACPI entry for cr50
This adds coreboot device tree entries on zoombini & meowth for the
cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This
is based on what we do for fizz.
BUG=b:71722449
TEST=booted to linux on meowth: tpm_version command now sees the cr50.
localhost ~ # tpm_version
TPM 2.0 Version Info:
Chip Version: 2.0.0.0
Spec Family: 322e3000
Spec Family String: 2.0
Spec Level: 0
Spec Revision: 116
Manufacturer Info: 43524f53
Manufacturer String: CROS
Vendor ID: xCG fTPM
TPM Model: 00000001
Firmware Version: 0ad551830bcf7a82
localhost ~ # uname -a
Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux
localhost ~ #
and we see interrupts when talking to the cr50:
localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru
pts
84: 4687 IO-APIC 84-edge cr50_spi
TPM 2.0 Version Info:
Chip Version: 2.0.0.0
Spec Family: 322e3000
Spec Family String: 2.0
Spec Level: 0
Spec Revision: 116
Manufacturer Info: 43524f53
Manufacturer String: CROS
Vendor ID: xCG fTPM
TPM Model: 00000001
Firmware Version: 0ad551830bcf7a82
84: 4799 IO-APIC 84-edge cr50_spi
localhost ~ #
Change-Id: I9d503334502503ef49515e4a8736d967bc454a98
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard')
4 files changed, 26 insertions, 6 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index da40baf1d9..44ea0bb5e1 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -91,7 +91,14 @@ chip soc/intel/cannonlake device pci 1d.7 off end # PCI Express Port 16 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 on end # GSPI #0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)" + device spi 0 on end + end + end # GSPI #0 device pci 1e.3 on end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/baseboard/gpio.c index 1626c38403..47894d020f 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/gpio.c +++ b/src/mainboard/google/zoombini/variants/baseboard/gpio.c @@ -89,7 +89,8 @@ static const struct pad_config gpio_table[] = { /* UART0_TXD */ /* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_NC(GPP_C11, NONE), -/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* H1_PCH_INT_ODL */ +/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE, + INVERT), /* H1_PCH_INT_ODL */ /* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* TRACKPAD_INT_ODL */ /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* TOUCHSCREEN_INT_ODL */ @@ -250,6 +251,8 @@ static const struct pad_config early_gpio_table[] = { /* Ensure UART pins are in native mode for H1. */ /* UART0_RXD */ /* UART_PCH_RX_DEBUG_TX */ /* UART0_TXD */ /* UART_PCH_RX_DEBUG_RX */ +/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE, + INVERT), /* H1_PCH_INT_ODL */ }; const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 2317c90b50..aed4a19527 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -97,7 +97,14 @@ chip soc/intel/cannonlake device pci 1d.7 off end # PCI Express Port 16 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 on end # GSPI #0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)" + device spi 0 on end + end + end # GSPI #0 device pci 1e.3 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index 790567f150..e0eaa9d259 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -98,8 +98,9 @@ static const struct pad_config gpio_table[] = { NF1), /* UART_PCH_TX_DEBUG_RX */ /* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 0, DEEP), /* PP3300_TOUCH_EN */ /* UART0_CTS# */ PAD_NC(GPP_C11, NONE), -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - LEVEL), /* H1_PCH_INT_ODL */ +/* Only P0 boards need an internal pullup */ +/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE, + INVERT), /* H1_PCH_INT_ODL */ /* UART1_TXD */ PAD_NC(GPP_C13, NONE), /* UART1_RTS# */ PAD_CFG_GPI_SCI(GPP_C14, NONE, DEEP, EDGE_SINGLE, NONE), /* TOUCHSCREEN_INT_ODL */ @@ -271,7 +272,9 @@ static const struct pad_config early_gpio_table[] = { /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), #endif -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, LEVEL), +/* Only P0 boards need an internal pullup */ +/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE, + INVERT), /* H1_PCH_INT_ODL */ }; const struct pad_config *variant_gpio_table(size_t *num) |