brya: add various ES variants

Fork multiple "4ES" variants off some brya devices to
properly support ES SoC.

BRANCH=none
BUG=b:201767461
TEST=emerge-brya coreboot and check the artifacts

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

62 files changed, 4936 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 6231762130..a5ca94209d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -104,26 +104,38 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Brya" if BOARD_GOOGLE_BRYA0
+	default "Brya4ES" if BOARD_GOOGLE_BRYA4ES
 	default "Brask" if BOARD_GOOGLE_BRASK
 	default "Primus" if BOARD_GOOGLE_PRIMUS
+	default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES
 	default "Gimble" if BOARD_GOOGLE_GIMBLE
+	default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES
 	default "Redrix" if BOARD_GOOGLE_REDRIX
+	default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES
 	default "Kano" if BOARD_GOOGLE_KANO
 	default "Taeko" if BOARD_GOOGLE_TAEKO
+	default "Taeko4ES" if BOARD_GOOGLE_TAEKO4ES
 	default "Felwinter" if BOARD_GOOGLE_FELWINTER
 	default "Anahera" if BOARD_GOOGLE_ANAHERA
+	default "Anahera4ES" if BOARD_GOOGLE_ANAHERA4ES
 	default "Vell" if BOARD_GOOGLE_VELL
 
 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
+	default "brya4es" if BOARD_GOOGLE_BRYA4ES
 	default "brask" if BOARD_GOOGLE_BRASK
 	default "primus" if BOARD_GOOGLE_PRIMUS
+	default "primus4es" if BOARD_GOOGLE_PRIMUS4ES
 	default "gimble" if BOARD_GOOGLE_GIMBLE
+	default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES
 	default "redrix" if BOARD_GOOGLE_REDRIX
+	default "redrix4es" if BOARD_GOOGLE_REDRIX4ES
 	default "kano" if BOARD_GOOGLE_KANO
 	default "taeko" if BOARD_GOOGLE_TAEKO
+	default "taeko4es" if BOARD_GOOGLE_TAEKO4ES
 	default "felwinter" if BOARD_GOOGLE_FELWINTER
 	default "anahera" if BOARD_GOOGLE_ANAHERA
+	default "anahera4es" if BOARD_GOOGLE_ANAHERA4ES
 	default "vell" if BOARD_GOOGLE_VELL
 
 config VBOOT
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 92b71a878c..804117165c 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -10,6 +10,16 @@ config BOARD_GOOGLE_BRYA0
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_CRASHLOG
 
+config BOARD_GOOGLE_BRYA4ES
+	bool "->  Brya4ES"
+	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select HAVE_WWAN_POWER_SEQUENCE
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_CRASHLOG
+
 config BOARD_GOOGLE_BRASK
 	bool "->  Brask"
 	select BOARD_GOOGLE_BASEBOARD_BRASK
@@ -24,6 +34,13 @@ config BOARD_GOOGLE_PRIMUS
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select HAVE_WWAN_POWER_SEQUENCE
 
+config BOARD_GOOGLE_PRIMUS4ES
+	bool "->  Primus4ES"
+	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select HAVE_WWAN_POWER_SEQUENCE
+
 config BOARD_GOOGLE_GIMBLE
 	bool "->  Gimble"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -32,6 +49,14 @@ config BOARD_GOOGLE_GIMBLE
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_I2C_MAX98390
 
+config BOARD_GOOGLE_GIMBLE4ES
+	bool "->  Gimble4ES"
+	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select CHROMEOS_DSM_CALIB if CHROMEOS
+	select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS
+	select DRIVERS_GENESYSLOGIC_GL9750
+	select DRIVERS_I2C_MAX98390
+
 config BOARD_GOOGLE_REDRIX
 	bool "->  Redrix"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -46,6 +71,20 @@ config BOARD_GOOGLE_REDRIX
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select HAVE_WWAN_POWER_SEQUENCE
 
+config BOARD_GOOGLE_REDRIX4ES
+	bool "->  Redrix4ES"
+	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select CHROMEOS_DSM_CALIB if CHROMEOS
+	select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS
+	select DRIVERS_I2C_MAX98390
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select DRIVERS_GENESYSLOGIC_GL9755
+	select DRIVERS_GFX_GENERIC
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select HAVE_WWAN_POWER_SEQUENCE
+
 config BOARD_GOOGLE_KANO
 	bool "->  Kano"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -60,6 +99,11 @@ config BOARD_GOOGLE_TAEKO
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENESYSLOGIC_GL9763E
 
+config BOARD_GOOGLE_TAEKO4ES
+	bool "->  Taeko4ES"
+	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select DRIVERS_GENESYSLOGIC_GL9763E
+
 config BOARD_GOOGLE_FELWINTER
 	bool "->  Felwinter"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -72,6 +116,13 @@ config BOARD_GOOGLE_ANAHERA
 	select DRIVERS_GFX_GENERIC
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
+config BOARD_GOOGLE_ANAHERA4ES
+	bool "->  Anahera4ES"
+	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select DRIVERS_GENESYSLOGIC_GL9763E
+	select DRIVERS_GFX_GENERIC
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
 config BOARD_GOOGLE_VELL
 	bool "->  Vell"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/anahera4es/Makefile.inc b/src/mainboard/google/brya/variants/anahera4es/Makefile.inc
new file mode 100644
index 0000000000..f2a624c0e8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/anahera4es/fw_config.c b/src/mainboard/google/brya/variants/anahera4es/fw_config.c
new file mode 100644
index 0000000000..b12293f3be
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/fw_config.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),	/* DMIC_CLK0 */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),	/* DMIC_DATA0 */
+
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),	/* I2S_SPKR_SCLK */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),	/* I2S_SPKR_SFRM */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),	/* I2S_PCH_TX_SPKR_RX */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),	/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) ||
+		fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682IVS_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c
new file mode 100644
index 0000000000..4ab457bdeb
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A7  : SRCCLK_OE7# ==> NC */
+	PAD_NC(GPP_A7, NONE),
+	/* A17 : DISP_MISCC ==> NC */
+	PAD_NC(GPP_A17, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B3  : PROC_GP2 ==> eMMC_PERST_L */
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	/* B5  : ISH_I2C0_SDA ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : ISH_I2C0_SCL ==> NC */
+	PAD_NC(GPP_B6, NONE),
+	/* B15  : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC(GPP_D3, NONE),
+	/* D5  : SRCCLKREQ0# ==> NC */
+	PAD_NC(GPP_D5, NONE),
+	/* D7  : SRCCLKREQ2# ==> NC */
+	PAD_NC(GPP_D7, NONE),
+	/* D13 : ISH_UART0_RXD ==> NC */
+	PAD_NC(GPP_D13, NONE),
+	/* D14 : ISH_UART0_TXD ==> NC */
+	PAD_NC(GPP_D14, NONE),
+	/* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
+	PAD_CFG_GPO(GPP_D15, 1, DEEP),
+	/* D16 : ISH_UART0_CTS# ==> NC */
+	PAD_NC(GPP_D16, NONE),
+	/* D17 : UART1_RXD ==> NC */
+	PAD_NC(GPP_D17, NONE),
+
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E0, 1, PLTRST),
+	/* E3  : PROC_GP0 ==> NC */
+	PAD_NC(GPP_E3, NONE),
+	/* E7  : PROC_GP1 ==> NC */
+	PAD_NC(GPP_E7, NONE),
+	/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+
+	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+	PAD_CFG_GPO(GPP_E20, 1, DEEP),
+	/* E23 : DDPA_CTRLDATA ==> NC */
+	PAD_NC(GPP_E23, NONE),
+
+	/* F20 : EXT_PWR_GATE# ==> NC */
+	PAD_NC(GPP_F20, NONE),
+
+	/* H20 : IMGCLKOUT1 ==> NC */
+	PAD_NC(GPP_H20, NONE),
+	/* H21 : IMGCLKOUT2 ==> Privacy screen */
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+	/* H23 : SRCCLKREQ5# ==> NC */
+	PAD_NC(GPP_H23, NONE),
+
+	/* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
+	PAD_NC(GPP_R7, NONE),
+
+	/* S4 : SNDW2_CLK ==> NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5 : SNDW2_DATA ==> NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L  */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */
+	PAD_CFG_GPO(GPP_E20, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h b/src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc
new file mode 100644
index 0000000000..68aa2f02ca
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A
diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..dcc5ba3433
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT53E1G32D2NP-046 WT:A         0 (0000)
+H9HCNNNBKMMLXR-NEE             1 (0001)
+K4U6E3S4AA-MGCR                1 (0001)
+MT53E512M32D2NP-046 WT:E       1 (0001)
+H9HCNNNCPMMLXR-NEE             2 (0010)
+K4UBE3D4AA-MGCR                2 (0010)
+H9HCNNNFAMMLXR-NEE             3 (0011)
+MT53E2G32D4NQ-046 WT:A         4 (0100)
+MT53E512M32D1NP-046 WT:B       1 (0001)
+MT53E1G32D2NP-046 WT:B         2 (0010)
diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..71bd5fd385
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
@@ -0,0 +1,10 @@
+MT53E1G32D2NP-046 WT:A
+H9HCNNNBKMMLXR-NEE
+K4U6E3S4AA-MGCR
+MT53E512M32D2NP-046 WT:E
+H9HCNNNCPMMLXR-NEE
+K4UBE3D4AA-MGCR
+H9HCNNNFAMMLXR-NEE
+MT53E2G32D4NQ-046 WT:A
+MT53E512M32D1NP-046 WT:B
+MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
new file mode 100644
index 0000000000..dc563a4c61
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -0,0 +1,378 @@
+fw_config
+	field DB_SD 0 1
+		option SD_ABSENT		0
+		option SD_GL9750		1
+	end
+	field KB_BL 2 2
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field AUDIO 3 5
+		option AUDIO_UNKNOWN		0
+		option MAX98360_ALC5682I_I2S	1
+		option MAX98360_ALC5682IVS_I2S	2
+	end
+	field DB_LTE 6 7
+		option LTE_ABSENT		0
+		option LTE_USB			1
+	end
+	field EPS 10 10
+		option PRIVACY_SCREEN_ABSENT	0
+		option PRIVACY_SCREEN		1
+	end
+end
+chip soc/intel/alderlake
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              |                           |
+	#| I2C3              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A MLB Port
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"     # Smart Card
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				register "device[0].name" = ""LCD""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].addr" = "0x80010400"
+				register "device[0].privacy.enabled" = "1"
+				register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)"
+				device generic 0 on
+					probe EPS PRIVACY_SCREEN
+				end
+			 end
+                end # Integrated Graphics Device
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Soc""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""Regulator""
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+					[4] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_3, 75, 5000),
+				}"
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,	85, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,	85, SHUTDOWN),
+				}"
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 off end
+		device ref pcie_rp7 on
+			# Enable PCIE eMMC bridge 7 using clk 6
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+			}"
+		end     #PCIE7 EMMC
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98360_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+                                        probe AUDIO MAX98360_ALC5682IVS_I2S
+				end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "reset_delay_ms" = "100"
+				register "reset_off_delay_ms" = "5"
+				register "enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "enable_delay_ms" = "10"
+				register "enable_off_delay_ms" = "1"
+				register "stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "50"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 40 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "3"
+						register "usb3_port_number" = "3"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref usb2_port2 on end
+                                        end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/brya4es/Makefile.inc b/src/mainboard/google/brya/variants/brya4es/Makefile.inc
new file mode 100644
index 0000000000..52d03980da
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/brya4es/fw_config.c b/src/mainboard/google/brya/variants/brya4es/fw_config.c
new file mode 100644
index 0000000000..17d284aa29
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/fw_config.c
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),	/* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),	/* DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+};
+
+static const struct pad_config sndw_enable_pads[] = {
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),	/* SDW_HP_CLK_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),	/* SDW_HP_DATA_R */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),	/* SDW_SPKR_CLK */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),	/* SDW_SPKR_DATA */
+};
+
+static const struct pad_config sndw_disable_pads[] = {
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+};
+
+static const struct pad_config i2s0_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+};
+
+static const struct pad_config i2s2_enable_pads[] = {
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),	/* I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),	/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s0_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+};
+
+static const struct pad_config i2s2_disable_pads[] = {
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void enable_i2s(void)
+{
+	gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+	gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
+	gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads));
+	gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
+}
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
+		gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) {
+		printk(BIOS_INFO, "Configure audio over SoundWire with MAX98373 ALC5682.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
+		gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	} else {
+		printk(BIOS_INFO, "BT offload disabled\n");
+		gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
+		gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n");
+		enable_i2s();
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, ALC1019_NAU88L25B_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n");
+		enable_i2s();
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c
new file mode 100644
index 0000000000..c3cfc0c3d4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/gpio.c
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <string.h>
+
+static const struct pad_config board_id0_1_overrides[] = {
+	/* B2  : VRALERT# ==> NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B15 : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+	/* C3  : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4  : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+	/* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
+	/* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
+	/* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
+	PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
+	/* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
+	PAD_NC(GPP_F21, NONE),
+	/* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
+	PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
+	/* GPD2: LAN_WAKE# ==> NC */
+	PAD_NC(GPD2, NONE),
+};
+
+/* Early pad configuration in bootblock for board id < 2 */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+/* Early pad configuration in bootblock for board id 2 */
+static const struct pad_config early_gpio_table_id2[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(board_id0_1_overrides);
+		return board_id0_1_overrides;
+	}
+
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(early_gpio_table);
+		return early_gpio_table;
+	}
+
+	*num = ARRAY_SIZE(early_gpio_table_id2);
+	return early_gpio_table_id2;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/brya4es/include/variant/ec.h b/src/mainboard/google/brya/variants/brya4es/include/variant/ec.h
new file mode 100644
index 0000000000..4fc0622f15
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h
new file mode 100644
index 0000000000..23338de2d8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_E16
+#define WWAN_PERST	GPP_E0
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc
new file mode 100644
index 0000000000..70c8d17adb
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/brya0/memory src/mainboard/google/brya/variants/brya0/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 2(0b0010)  Parts = MT53E2G32D4NQ-046 WT:A
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..bfc1ead13f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/brya0/memory src/mainboard/google/brya/variants/brya0/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:F       0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E1G32D2NP-046 WT:A         1 (0001)
+MT53E2G32D4NQ-046 WT:A         2 (0010)
+H9HCNNNCPMMLXR-NEE             3 (0011)
+MT53E1G32D2NP-046 WT:B         3 (0011)
diff --git a/src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..c8a24ccd6d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt
@@ -0,0 +1,6 @@
+MT53E512M32D2NP-046 WT:F
+H9HCNNNBKMMLXR-NEE
+MT53E1G32D2NP-046 WT:A
+MT53E2G32D4NQ-046 WT:A
+H9HCNNNCPMMLXR-NEE
+MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
new file mode 100644
index 0000000000..6812f20ad2
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
@@ -0,0 +1,742 @@
+fw_config
+	field DB_USB 0 3
+		option USB_ABSENT		0
+		option USB3_PS8815		1
+	end
+	field DB_SD 4 5
+		option SD_ABSENT		0
+		option SD_GL9755S		1
+	end
+	field KB_BL 7 7
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field AUDIO 8 10
+		option AUDIO_UNKNOWN		0
+		option MAX98357_ALC5682I_I2S	1
+		option MAX98373_ALC5682_SNDW	2
+		option MAX98373_NAU88L25B_I2S	3
+		option ALC1019_NAU88L25B_I2S	4
+	end
+	field DB_LTE 11 12
+		option LTE_ABSENT		0
+		option LTE_USB			1
+		option LTE_PCIE			2
+	end
+	field UFC 13 14
+		option UFC_USB			0
+		option UFC_MIPI_IMX208		1
+	end
+	# Bits 15 and 16 were intended for WFC but never declared here
+	field HPS 17 17
+		option HPS_ABSENT               0
+		option HPS_PRESENT              1
+	end
+end
+
+chip soc/intel/alderlake
+	register "SaGv" = "SaGv_Enabled"
+
+	register "PsysPmax" = "145"
+
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A MLB Port
+
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
+	# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
+	# bypass rails implemented.
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""WWAN""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+								TEMP_PCT(70, 50),
+								TEMP_PCT(65, 30),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_1,
+						.thresholds = {
+								TEMP_PCT(50, 90),
+								TEMP_PCT(48, 70),
+								TEMP_PCT(46, 60),
+								TEMP_PCT(43, 40),
+								TEMP_PCT(40, 30),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 75, 5000),
+					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
+				register "cio2_prt[0]" = "2"
+				device generic 0 on
+					# MIPI lanes are split between UFC and WFC depending on
+					# whether the UFC is USB or MIPI hence probing UFC_USB
+					probe UFC UFC_USB
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
+				register "cio2_prt[0]" = "2"
+				register "cio2_prt[1]" = "1"
+				device generic 1 on
+					probe UFC UFC_MIPI_IMX208
+				end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			probe DB_LTE LTE_PCIE
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98357_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/nau8825
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+				register "jkdet_enable" = "1"
+				register "jkdet_pull_enable" = "0"
+				register "jkdet_polarity" = "1"		# ActiveLow
+				register "vref_impedance" = "2"		# 125kOhm
+				register "micbias_voltage" = "6"	# 2.754
+				register "sar_threshold_num" = "4"
+				register "sar_threshold[0]" = "0x0c"
+				register "sar_threshold[1]" = "0x1c"
+				register "sar_threshold[2]" = "0x38"
+				register "sar_threshold[3]" = "0x60"
+				register "sar_hysteresis" = "1"
+				register "sar_voltage" = "0"		# VDDA
+				register "sar_compare_time" = "0"	# 500ns
+				register "sar_sampling_time" = "0"	# 2us
+				register "short_key_debounce" = "2"	# 100ms
+				register "jack_insert_debounce" = "7"	# 512ms
+				register "jack_eject_debounce" = "7"	# 512ms
+				device i2c 1a on
+					probe AUDIO ALC1019_NAU88L25B_I2S
+				end
+			end
+			chip drivers/generic/alc1015
+				register "hid" = ""RTL1019""
+				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				device generic 1 on
+					probe AUDIO ALC1019_NAU88L25B_I2S
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "0"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "360 * MHz" # 360 MHz
+				register "link_freq[1]" = "180 * MHz" # 180 MHz
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 10 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "2"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW9768 VCM""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9768""
+
+				device i2c 0C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""AT24 EEPROM""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC""
+				register "nvm_compat" = ""atmel,24c1024""
+
+				register "nvm_size" = "0x2800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x10"
+
+				device i2c 58 on end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9050""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x5d on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SIS9815""
+				register "generic.desc" = ""SIS Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "100"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "7"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x00"
+				device i2c 5c on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR1 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x00"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x07"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x07"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0f"
+				register "reg_prox_ctrl0" = "0x12"
+				register "reg_prox_ctrl1" = "0x12"
+				register "reg_prox_ctrl2" = "0x90"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x12"
+				register "reg_prox_ctrl6" = "0x3c"
+				register "reg_prox_ctrl7" = "0x58"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x5c"
+				register "reg_adv_ctrl11" = "0x52"
+				register "reg_adv_ctrl12" = "0xb5"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x38"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0xf0"
+				register "reg_adv_ctrl20" = "0xf0"
+				device i2c 28 on end
+			end
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR2 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "2"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x00"
+				register "reg_afe_ctrl1" = "0x10"
+				register "reg_afe_ctrl2" = "0x00"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x07"
+				register "reg_afe_ctrl5" = "0x00"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x07"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0f"
+				register "reg_prox_ctrl0" = "0x12"
+				register "reg_prox_ctrl1" = "0x12"
+				register "reg_prox_ctrl2" = "0x90"
+				register "reg_prox_ctrl3" = "0x60"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x12"
+				register "reg_prox_ctrl6" = "0x3c"
+				register "reg_prox_ctrl7" = "0x58"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x5c"
+				register "reg_adv_ctrl11" = "0x52"
+				register "reg_adv_ctrl12" = "0xb5"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x38"
+				register "reg_adv_ctrl17" = "0x56"
+				register "reg_adv_ctrl18" = "0x33"
+				register "reg_adv_ctrl19" = "0xf0"
+				register "reg_adv_ctrl20" = "0xf0"
+				device i2c 2C on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3478""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""imx 208 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "384 * MHz" # 384 MHz
+				register "link_freq[1]" = "96 * MHz" # 96 MHz
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_C3"  #PP3300_FCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset
+				register "gpio_panel.gpio[3].gpio_num" = "GPP_H21" #CLK_EN
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(3, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(3, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 10 on
+					probe UFC UFC_MIPI_IMX208
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3499""
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM1""
+				register "chip_name" = ""GT24C16S""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+
+				register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC""
+
+				register "nvm_size" = "0x2800"
+				register "nvm_pagesize" = "0x01"
+				register "nvm_readonly" = "0x01"
+				register "nvm_width" = "0x0E"
+
+				device i2c 50 on
+					probe UFC UFC_MIPI_IMX208
+				end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""GOOG0020""
+				register "desc" = ""Chrome OS HPS""
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"  # EN_HPS_PWR
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)"  # HPS_INT_ODL
+				# HPS uses I2C addresses 0x30 and 0x51.
+				# The address we provide here is not significant because
+				# neither coreboot nor Linux have a driver for HPS,
+				# it's only used from userspace.
+				device i2c 30 on
+					probe HPS HPS_PRESENT
+				end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98357A""
+				register "sdmode_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO MAX98357_ALC5682I_I2S
+				end
+			end
+
+			chip drivers/intel/soundwire
+				device generic 0 on
+					probe AUDIO MAX98373_ALC5682_SNDW
+					chip drivers/soundwire/alc5682
+						# SoundWire Link 0 ID 1
+						register "desc" = ""Headset Codec""
+						device generic 0.1 on end
+					end
+					chip drivers/soundwire/max98373
+						# SoundWire Link 2 ID 3
+						register "desc" = ""Left Speaker Amp""
+						device generic 2.3 on end
+					end
+					chip drivers/soundwire/max98373
+						# SoundWire Link 2 ID 7
+						register "desc" = ""Right Speaker Amp""
+						device generic 2.7 on end
+					end
+				end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				use conn2 as mux_conn[2]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "2"
+						register "usb3_port_number" = "2"
+						device generic 1 alias conn1 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "3"
+						register "usb3_port_number" = "3"
+						device generic 2 alias conn2 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on
+							probe UFC UFC_USB
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/brya4es/ramstage.c b/src/mainboard/google/brya/variants/brya4es/ramstage.c
new file mode 100644
index 0000000000..06040e485f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/ramstage.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	/* All values are for baseline config as per bug:191906315 comment #10 */
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}
diff --git a/src/mainboard/google/brya/variants/brya4es/variant.c b/src/mainboard/google/brya/variants/brya4es/variant.c
new file mode 100644
index 0000000000..8d4471ba2e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brya4es/variant.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW));
+}
diff --git a/src/mainboard/google/brya/variants/gimble4es/Makefile.inc b/src/mainboard/google/brya/variants/gimble4es/Makefile.inc
new file mode 100644
index 0000000000..446d113a80
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/Makefile.inc
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/gimble4es/fw_config.c b/src/mainboard/google/brya/variants/gimble4es/fw_config.c
new file mode 100644
index 0000000000..e9d87b33d8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/fw_config.c
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),	/* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),	/* DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),	/* I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),	/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_SSP1))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c
new file mode 100644
index 0000000000..2ea9f90995
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A6  : ESPI_ALERT1# ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : SRCCLK_OE7# ==> NC */
+	PAD_NC(GPP_A7, NONE),
+	/* A8  : SRCCLKREQ7# ==> NC */
+	PAD_NC(GPP_A8, NONE),
+	/* A12 : SATAXPCIE1 ==>  NC  */
+	PAD_NC(GPP_A12, NONE),
+	/* A14 : USB_OC1# ==> NC */
+	PAD_NC(GPP_A14, NONE),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A18 : DDSP_HPDB ==> NC */
+	PAD_NC(GPP_A18, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B3  : PROC_GP2 ==> NC */
+	PAD_NC(GPP_B3, NONE),
+	/* B5  : ISH_I2C0_SDA ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : ISH_I2C0_SCL ==> NC */
+	PAD_NC(GPP_B6, NONE),
+
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC(GPP_D3, NONE),
+	/* D5  : SRCCLKREQ0# ==> NC */
+	PAD_NC(GPP_D5, NONE),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC(GPP_D9, NONE),
+	/* D15 : ISH_UART0_RTS# ==> NC */
+	PAD_NC(GPP_D15, NONE),
+	/* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+	/* D17 : UART1_RXD ==> NC */
+	PAD_NC(GPP_D17, NONE),
+
+	/* E0  : SATAXPCIE0 ==> NC */
+	PAD_NC(GPP_E0, NONE),
+	/* E3  : PROC_GP0 ==> NC */
+	PAD_NC(GPP_E3, NONE),
+	/* E4  : SATA_DEVSLP0 ==> NC */
+	PAD_NC(GPP_E4, NONE),
+	/* E7  : PROC_GP1 ==> NC */
+	PAD_NC(GPP_E7, NONE),
+	/* E10 : THC0_SPI1_CS# ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* E16 : RSVD_TP ==> NC */
+	PAD_NC(GPP_E16, NONE),
+	/* E17 : THC0_SPI1_INT# ==> NC */
+	PAD_NC(GPP_E17, NONE),
+	/* E18 : DDP1_CTRLCLK ==> NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+
+	/* F6  : CNV_PA_BLANKING ==> NC */
+	PAD_NC(GPP_F6, NONE),
+	/* F19 : SRCCLKREQ6# ==> NC */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : EXT_PWR_GATE# ==> NC */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
+
+	/* H8  : I2C4_SDA ==> NC */
+	PAD_NC(GPP_H8, NONE),
+	/* H9  : I2C4_SCL ==> NC */
+	PAD_NC(GPP_H9, NONE),
+	/* H15 : DDPB_CTRLCLK ==> NC */
+	PAD_NC(GPP_H15, NONE),
+	/* H17 : DDPB_CTRLDATA ==> NC*/
+	PAD_NC(GPP_H17, NONE),
+	/* H19 : SRCCLKREQ4# ==> NC */
+	PAD_NC(GPP_H19, NONE),
+	/* H21 : IMGCLKOUT2 ==> NC */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+	/* H23 : SRCCLKREQ5# ==> NC */
+	PAD_NC(GPP_H23, NONE),
+
+	/* S4 : SNDW2_CLK ==> NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5 : SNDW2_DATA ==> NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+
+	/* GPD11: LANPHYC ==> NC */
+	PAD_NC(GPD11, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+
+	/* E0  : SATAXPCIE0 ==> NC */
+	PAD_NC(GPP_E0, NONE),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E16 : RSVD_TP ==> NC */
+	PAD_NC(GPP_E16, NONE),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc
new file mode 100644
index 0000000000..9db94849fc
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/gimble/memory src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 1(0b0001)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 2(0b0010)  Parts = MT53E1G32D2NP-046 WT:A
diff --git a/src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..c3a1347f74
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/gimble/memory src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:E       0 (0000)
+H9HCNNNCPMMLXR-NEE             1 (0001)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E1G32D2NP-046 WT:A         2 (0010)
+K4U6E3S4AA-MGCR                0 (0000)
+K4UBE3D4AA-MGCR                1 (0001)
+MT53E512M32D1NP-046 WT:B       0 (0000)
+MT53E1G32D2NP-046 WT:B         1 (0001)
diff --git a/src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..568e7246a4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt
@@ -0,0 +1,8 @@
+MT53E512M32D2NP-046 WT:E
+H9HCNNNCPMMLXR-NEE
+H9HCNNNBKMMLXR-NEE
+MT53E1G32D2NP-046 WT:A
+K4U6E3S4AA-MGCR
+K4UBE3D4AA-MGCR
+MT53E512M32D1NP-046 WT:B
+MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
new file mode 100644
index 0000000000..8b6daf2b29
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
@@ -0,0 +1,292 @@
+fw_config
+	field DB_USB 0 3
+		option USB_ABSENT			0
+		option USB3_PS8815			1
+	end
+	field DB_SD 4 5
+		option SD_ABSENT			0
+		option SD_GL9750H			1
+	end
+	field KB_BL 7 7
+		option KB_BL_ABSENT			0
+		option KB_BL_PRESENT			1
+	end
+	field AUDIO 8 10
+		option AUDIO_UNKNOWN			0
+		option MAX98390_ALC5682I_I2S		1
+		option MAX98390_ALC5682I_I2S_SSP1	2
+	end
+	field DB_LTE 11 12
+		option LTE_ABSENT			0
+	end
+end
+chip soc/intel/alderlake
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+	register "SaGv" = "SaGv_Enabled"
+	register "TcssAuxOri" = "1"
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+	register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Fan""
+				register "options.tsr[2].desc" = ""Charger""
+				# TODO: below values are initial reference values only
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+				}"
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 12000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98390_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98390_ALC5682I_I2S_SSP1
+				end
+			end
+			chip drivers/i2c/max98390
+				register "desc" = ""MAX98390 Speaker Amp 0""
+				register "uid" = "0"
+				register "name" = ""MXW0""
+				register "r0_calib_key" = ""dsm_calib_r0_0""
+				register "temperature_calib_key" = ""dsm_calib_temp_0""
+				register "dsm_param_file_name" = ""dsm_param_R""
+				register "vmon_slot_no" = "0"
+				register "imon_slot_no" = "1"
+				device i2c 0x38 on
+				end
+			end
+			chip drivers/i2c/max98390
+				register "desc" = ""MAX98390 Speaker Amp 1""
+				register "uid" = "1"
+				register "name" = ""MXW1""
+				register "r0_calib_key" = ""dsm_calib_r0_1""
+				register "temperature_calib_key" = ""dsm_calib_temp_1""
+				register "dsm_param_file_name" = ""dsm_param_L""
+				register "vmon_slot_no" = "1"
+				register "imon_slot_no" = "0"
+				device i2c 0x3c on
+				end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9050""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x15 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 0x15 on end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "2"
+						register "usb3_port_number" = "3"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "privacy_gpio"  = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D13)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb3_port2 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/gimble4es/variant.c b/src/mainboard/google/brya/variants/gimble4es/variant.c
new file mode 100644
index 0000000000..96ccf88ae7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gimble4es/variant.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <sar.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO,
+							MAX98390_ALC5682I_I2S_SSP1));
+}
diff --git a/src/mainboard/google/brya/variants/primus4es/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/Makefile.inc
new file mode 100644
index 0000000000..725b883fba
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/primus4es/fw_config.c b/src/mainboard/google/brya/variants/primus4es/fw_config.c
new file mode 100644
index 0000000000..c9b4a38be5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/fw_config.c
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),	/* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),	/* DMIC_DATA0_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),	/* DMIC_CLK1_R */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),	/* DMIC_DATA1_R */
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),	/* I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),	/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static const struct pad_config bt_i2s_disable_pads[] = {
+	PAD_NC(GPP_VGPIO_30, NONE),
+	PAD_NC(GPP_VGPIO_31, NONE),
+	PAD_NC(GPP_VGPIO_32, NONE),
+	PAD_NC(GPP_VGPIO_33, NONE),
+	PAD_NC(GPP_VGPIO_34, NONE),
+	PAD_NC(GPP_VGPIO_35, NONE),
+	PAD_NC(GPP_VGPIO_36, NONE),
+	PAD_NC(GPP_VGPIO_37, NONE),
+};
+
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I-VS.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c
new file mode 100644
index 0000000000..df0930c42f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/gpio.c
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A6  : ESPI_ALERT1# ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : SRCCLK_OE7# ==> NC */
+	PAD_NC(GPP_A7, NONE),
+	/* A14 : USB_OC1# ==> NC */
+	PAD_NC(GPP_A14, NONE),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B3  : PROC_GP2 ==> eMMC_PERST_L */
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+
+	/* D3  : ISH_GP3 ==> M2_SSD_PLN_L */
+	PAD_CFG_GPO(GPP_D3, 1, PLTRST),
+	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6  : SRCCLKREQ1# ==> NC */
+	PAD_NC(GPP_D6, NONE),
+	/* D13 : ISH_UART0_RXD ==> NC */
+	PAD_NC(GPP_D13, NONE),
+	/* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
+	PAD_CFG_GPO(GPP_D14, 1, DEEP),
+	/* D18 : UART1_TXD ==> SD_PE_RST_L */
+	PAD_CFG_GPO(GPP_D18, 1, PLTRST),
+
+	/* E3  : PROC_GP0 ==> NC */
+	PAD_NC(GPP_E3, NONE),
+	/* E7  : PROC_GP1 ==> NC */
+	PAD_NC(GPP_E7, NONE),
+
+	/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	/* F20 : EXT_PWR_GATE# ==> NC */
+	PAD_NC(GPP_F20, NONE),
+
+	/* H19 : SRCCLKREQ4# ==> NC */
+	PAD_NC(GPP_H19, NONE),
+	/* H21 : IMGCLKOUT2 ==> NC */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+	/* H23 : SRCCLKREQ5# ==> NC */
+	PAD_NC(GPP_H23, NONE),
+
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+
+	/* T2 : GPP_T2 ==> eMMC_CFG */
+	PAD_CFG_GPI(GPP_T2, NONE, DEEP),
+
+	/* GPD11: LANPHYC ==> NC */
+	PAD_NC(GPD11, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* D18 : UART1_TXD ==> SD_PE_RST_L */
+	PAD_CFG_GPO(GPP_D18, 0, PLTRST),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+	PAD_CFG_GPO(GPP_E20, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h b/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h
new file mode 100644
index 0000000000..7309098359
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+/* Enable PS/2 Mouse */
+#define SIO_EC_ENABLE_PS2M
+
+#endif
diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h
new file mode 100644
index 0000000000..cbf6040265
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_E16
+#define WWAN_PERST	GPP_E0
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+
+#endif
diff --git a/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc
new file mode 100644
index 0000000000..d2fae296db
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR
diff --git a/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..cdaaac01c6
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+H9HCNNNBKMMLXR-NEE             0 (0000)
+H9HCNNNFAMMLXR-NEE             1 (0001)
+H9HCNNNCPMMLXR-NEE             2 (0010)
+K4U6E3S4AA-MGCR                0 (0000)
+MT53E512M32D1NP-046 WT:B       0 (0000)
+MT53E1G32D2NP-046 WT:B         2 (0010)
+K4UBE3D4AA-MGCR                2 (0010)
diff --git a/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..bb14464356
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt
@@ -0,0 +1,7 @@
+H9HCNNNBKMMLXR-NEE
+H9HCNNNFAMMLXR-NEE
+H9HCNNNCPMMLXR-NEE
+K4U6E3S4AA-MGCR
+MT53E512M32D1NP-046 WT:B
+MT53E1G32D2NP-046 WT:B
+K4UBE3D4AA-MGCR
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
new file mode 100644
index 0000000000..c12939f4e8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
@@ -0,0 +1,390 @@
+fw_config
+	field DB_USB 0 3
+		option USB_ABSENT		0
+		option USB3_PS8811		1
+	end
+	field DB_SD 4 5
+		option SD_ABSENT		0
+		option SD_GL9755S		1
+	end
+	field KB_BL 7 7
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field AUDIO 8 10
+		option AUDIO_UNKNOWN		0
+		option MAX98360_ALC5682I_I2S	1
+		option MAX98360_ALC5682I_VS_I2S	2
+	end
+	field DB_LTE 11 12
+		option LTE_ABSENT		0
+		option LTE_USB			1
+	end
+end
+
+chip soc/intel/alderlake
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+	register "SaGv" = "SaGv_Enabled"
+	register "MaxDramSpeed" = "3733"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              |                           |
+	#| I2C3              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A MLB Port
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""SSD""
+				register "options.tsr[1].desc" = ""CHARGER""
+				register "options.tsr[2].desc" = ""MEMORY""
+				register "options.tsr[3].desc" = ""TYPEC""
+				# TODO: below values are initial reference values only
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,      CPU,               95, 5000),
+					[1] = DPTF_PASSIVE(CPU,      TEMP_SENSOR_0,     90, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,  TEMP_SENSOR_1,     90, 5000),
+					[3] = DPTF_PASSIVE(CPU,      TEMP_SENSOR_2,     90, 5000),
+					[4] = DPTF_PASSIVE(CPU,      TEMP_SENSOR_3,     90, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      89, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 250,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp3 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+				register "srcclk_pin" = "6"
+				device generic 0 alias emmc_rtd3 on end
+			end
+			# Enable PCIe-to-eMMC bridge PCIE 3 using clk 6
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE3 BH799BB
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 off end #PCIE6 WWAN
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			# Enable NVMe PCIE 9 using clk 0
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE9-12 SSD
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a alias audio_codec on
+					probe AUDIO MAX98360_ALC5682I_I2S
+					probe AUDIO MAX98360_ALC5682I_VS_I2S
+				end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9050""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "50"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x40 on end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GXTP7288""
+				register "generic.desc" = ""Goodix Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 2c on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO MAX98360_ALC5682I_I2S
+					probe AUDIO MAX98360_ALC5682I_VS_I2S
+				end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "3"
+						register "usb3_port_number" = "3"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/primus4es/variant.c b/src/mainboard/google/brya/variants/primus4es/variant.c
new file mode 100644
index 0000000000..4c2458acf7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus4es/variant.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <device/device.h>
+#include <drivers/i2c/hid/chip.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+
+static void devtree_update_emmc_rtd3(uint32_t board_ver)
+{
+	struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3);
+	if (board_ver > 1)
+		return;
+
+	emmc_rtd3->enabled = 0;
+}
+
+static void devtree_update_audio_codec(uint32_t board_ver)
+{
+	struct device *audio_codec = DEV_PTR(audio_codec);
+	struct drivers_i2c_generic_config *config = audio_codec->chip_info;
+
+	if (board_ver <= 1)
+		return;
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S)))
+		config->hid = "RTL5682";
+}
+
+static const struct pad_config nvme_disable_pads[] = {
+	PAD_NC(GPP_B2, NONE),	/* B2  : VRALERT# ==> M2_SSD_PLA_L */
+	PAD_NC(GPP_B4, NONE),	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_NC(GPP_D3, NONE),	/* D3  : ISH_GP3 ==> M2_SSD_PLN_L */
+	PAD_NC(GPP_D5, NONE),	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
+	PAD_NC(GPP_D11, NONE),	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+};
+
+static const struct pad_config emmc_disable_pads[] = {
+	PAD_NC(GPP_B3, NONE),	/* B3  : PROC_GP2 ==> eMMC_PERST_L */
+	PAD_NC(GPP_E20, NONE),	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+	PAD_NC(GPP_F19, NONE),	/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
+};
+
+static void disable_unused_gpios(void)
+{
+	int emmc_detected = gpio_get(GPP_T2);
+
+	if (emmc_detected == 1)
+		gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));
+	else
+		gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads));
+}
+
+void variant_devtree_update(void)
+{
+	uint32_t board_ver = board_id();
+	disable_unused_gpios();
+	devtree_update_emmc_rtd3(board_ver);
+	devtree_update_audio_codec(board_ver);
+}
diff --git a/src/mainboard/google/brya/variants/redrix4es/Makefile.inc b/src/mainboard/google/brya/variants/redrix4es/Makefile.inc
new file mode 100644
index 0000000000..446d113a80
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/Makefile.inc
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/redrix4es/fw_config.c b/src/mainboard/google/brya/variants/redrix4es/fw_config.c
new file mode 100644
index 0000000000..ac31d99c44
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/fw_config.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),	/* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),	/* DMIC_DATA0_R */
+
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),	/* I2S_PCH_TX_SPKR_RX_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),	/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+};
+
+static const struct pad_config bt_i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),	/* SSP_RXD */
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_4SPK))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+		printk(BIOS_INFO, "BT offload enabled\n");
+		gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c
new file mode 100644
index 0000000000..afcb7e9114
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A17 : DISP_MISCC ==> NC */
+	PAD_NC(GPP_A17, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B3  : PROC_GP2 ==> NC */
+	PAD_NC(GPP_B3, NONE),
+	/* B15  : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+
+	/* D7  : SRCCLKREQ2# ==> NC */
+	PAD_NC(GPP_D7, NONE),
+	/* D13 : ISH_UART0_RXD ==> NC */
+	PAD_NC(GPP_D13, NONE),
+
+	/* E3  : PROC_GP0 ==> NC */
+	PAD_NC(GPP_E3, NONE),
+	/* E7  : PROC_GP1 ==> NC */
+	PAD_NC(GPP_E7, NONE),
+	/* E16 : RSVD_TP ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E22 : DDPA_CTRLCLK ==> NC */
+	PAD_NC(GPP_E22, NONE),
+	/* E23 : DDPA_CTRLDATA ==> NC */
+	PAD_NC(GPP_E23, NONE),
+	/* F20 : EXT_PWR_GATE# ==> NC */
+	PAD_NC(GPP_F20, NONE),
+
+	/* H3  : SX_EXIT_HOLDOFF# ==> NC */
+	PAD_NC(GPP_H3, NONE),
+	/* H20 : IMGCLKOUT1 ==> NC */
+	PAD_NC(GPP_H20, NONE),
+	/* H21 : IMGCLKOUT2 ==> Privacy screen */
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+
+	/* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
+	PAD_NC(GPP_R7, NONE),
+
+	/* S4 : SNDW2_CLK ==> NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5 : SNDW2_DATA ==> NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+	/*
+	 * E0 : SATAXPCIE0 ==> WWAN_PERST_L
+	 * Drive high here, so that PERST_L is sequenced after RST_L
+	 */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/*
+	 * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
+	 * then deassert PERST# in romstage
+	 */
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h
new file mode 100644
index 0000000000..6f104d5da4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif
diff --git a/src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h
new file mode 100644
index 0000000000..99d09b2432
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_E16
+#define WWAN_PERST	GPP_E0
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+
+#endif
diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc
new file mode 100644
index 0000000000..8590598885
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A
diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..296634a290
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT53E1G32D2NP-046 WT:A         0 (0000)
+H9HCNNNBKMMLXR-NEE             1 (0001)
+K4U6E3S4AA-MGCR                1 (0001)
+MT53E512M32D2NP-046 WT:E       1 (0001)
+H9HCNNNCPMMLXR-NEE             2 (0010)
+K4UBE3D4AA-MGCR                2 (0010)
+H9HCNNNFAMMLXR-NEE             3 (0011)
+MT53E2G32D4NQ-046 WT:A         4 (0100)
+MT53E512M32D1NP-046 WT:B       1 (0001)
+MT53E1G32D2NP-046 WT:B         2 (0010)
diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..71bd5fd385
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
@@ -0,0 +1,10 @@
+MT53E1G32D2NP-046 WT:A
+H9HCNNNBKMMLXR-NEE
+K4U6E3S4AA-MGCR
+MT53E512M32D2NP-046 WT:E
+H9HCNNNCPMMLXR-NEE
+K4UBE3D4AA-MGCR
+H9HCNNNFAMMLXR-NEE
+MT53E2G32D4NQ-046 WT:A
+MT53E512M32D1NP-046 WT:B
+MT53E1G32D2NP-046 WT:B
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
new file mode 100644
index 0000000000..67cb7f3b74
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -0,0 +1,523 @@
+fw_config
+	field DB_SD 0 1
+		option SD_ABSENT		0
+		option SD_GL9755S		1
+	end
+	field KB_BL 2 2
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field AUDIO 3 5
+		option AUDIO_UNKNOWN			0
+		option MAX98390_ALC5682I_I2S_4SPK	1
+	end
+	field DB_LTE 6 7
+		option LTE_ABSENT		0
+		option LTE_USB			1
+		option LTE_PCIE			2
+	end
+	field EPS 10 10
+		option PRIVACY_SCREEN_ABSENT	0
+		option PRIVACY_SCREEN		1
+	end
+	field CAMERA_UFC 38 39
+		option CAMERA_NONE		0
+		option CAMERA_OV5675		1
+		option CAMERA_HI556		2
+	end
+	field TP_SOURCE 40 41
+		option ELAN0000			0
+		option ELAN2703			1
+	end
+end
+chip soc/intel/alderlake
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+	register "SaGv" = "SaGv_Enabled"
+	register "CnviBtAudioOffload" = "true"
+	# FIVR RFI Spread Spectrum 6%
+	register "FivrSpreadSpectrum" = "FIVR_SS_6"
+
+	# Acoustic settings
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              |                           |
+	#| I2C3              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "1"
+				register "device[0].name" = ""LCD""
+				# Internal panel on the first port of the graphics chip
+				register "device[0].addr" = "0x80010400"
+				register "device[0].privacy.enabled" = "1"
+				register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)"
+				device generic 0 on
+					probe EPS PRIVACY_SCREEN
+				end
+			end
+		end # Integrated Graphics Device
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""SOC""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""5V regulator""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           55, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 45, 5000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 51, 5000),
+					[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 51, 5000),
+					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 51, 5000),
+				}"
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 13000,
+							.max_power = 15000,
+							.time_window_min = 42 * MSECS_PER_SEC,
+							.time_window_max = 42 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 35000,
+							.max_power = 35000,
+							.time_window_min = 42 * MSECS_PER_SEC,
+							.time_window_max = 42 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
+				register "cio2_prt[0]" = "2"
+				device generic 0 on end
+			end
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			probe DB_LTE LTE_PCIE
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end	#PCIE8 SD card
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98390_ALC5682I_I2S_4SPK
+				end
+			end
+			chip drivers/i2c/max98390
+				register "desc" = ""MAX98390 Speaker Amp 0""
+				register "uid" = "0"
+				register "name" = ""MXW0""
+				register "r0_calib_key" = ""dsm_calib_r0_0""
+				register "temperature_calib_key" = ""dsm_calib_temp_0""
+				register "dsm_param_file_name" = ""dsm_param_R""
+				register "vmon_slot_no" = "0"
+				register "imon_slot_no" = "1"
+				device i2c 0x3a on
+					probe AUDIO MAX98390_ALC5682I_I2S_4SPK
+				end
+			end
+			chip drivers/i2c/max98390
+				register "desc" = ""MAX98390 Speaker Amp 1""
+				register "uid" = "1"
+				register "name" = ""MXW1""
+				register "r0_calib_key" = ""dsm_calib_r0_1""
+				register "temperature_calib_key" = ""dsm_calib_temp_1""
+				register "dsm_param_file_name" = ""dsm_param_L""
+				register "vmon_slot_no" = "1"
+				register "imon_slot_no" = "0"
+				device i2c 0x3b on
+					probe AUDIO MAX98390_ALC5682I_I2S_4SPK
+				end
+			end
+			chip drivers/i2c/max98390
+				register "desc" = ""MAX98390 Speaker Amp 2""
+				register "uid" = "2"
+				register "name" = ""MXW2""
+				register "r0_calib_key" = ""dsm_calib_r0_2""
+				register "temperature_calib_key" = ""dsm_calib_temp_2""
+				register "dsm_param_file_name" = ""dsm_param_tt_R""
+				register "vmon_slot_no" = "2"
+				register "imon_slot_no" = "3"
+				device i2c 0x38 on
+					probe AUDIO MAX98390_ALC5682I_I2S_4SPK
+				end
+			end
+			chip drivers/i2c/max98390
+				register "desc" = ""MAX98390 Speaker Amp 3""
+				register "uid" = "3"
+				register "name" = ""MXW3""
+				register "r0_calib_key" = ""dsm_calib_r0_3""
+				register "temperature_calib_key" = ""dsm_calib_temp_3""
+				register "dsm_param_file_name" = ""dsm_param_tt_L""
+				register "vmon_slot_no" = "3"
+				register "imon_slot_no" = "2"
+				device i2c 0x39 on
+					probe AUDIO MAX98390_ALC5682I_I2S_4SPK
+				end
+			end
+		end #I2C0
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2513""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "300"
+				register "generic.reset_off_delay_ms" = "1"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x15 on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
+				register "remote_name" = ""IPU0""
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  #EN_UCAM_LED_PWR
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+				device i2c 36 on
+					probe CAMERA_UFC CAMERA_NONE
+					probe CAMERA_UFC CAMERA_OV5675
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""INT3537""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Hi-556 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "437000000"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  #EN_UCAM_LED_PWR
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+				device i2c 20 on
+					probe CAMERA_UFC CAMERA_HI556
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""M24C64X""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_UCAM_PWR
+
+				#_ON
+				register "on_seq.ops_cnt" = "1"
+				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "1"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				register "nvm_size" = "0x2000"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x10"
+				register "nvm_compat" = ""atmel,24c64""
+				device i2c 50 on end
+			end
+
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 15 on
+					probe TP_SOURCE ELAN0000
+				end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2703""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on
+					probe TP_SOURCE ELAN2703
+				end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "3"
+						register "usb3_port_number" = "3"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/google/brya/variants/redrix4es/variant.c b/src/mainboard/google/brya/variants/redrix4es/variant.c
new file mode 100644
index 0000000000..6a79780f6e
--- /dev/null
+++ b/src/mainboard/google/brya/variants/redrix4es/variant.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return "wifi_sar_0.hex";
+}
diff --git a/src/mainboard/google/brya/variants/taeko4es/Makefile.inc b/src/mainboard/google/brya/variants/taeko4es/Makefile.inc
new file mode 100644
index 0000000000..478f362638
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/taeko4es/fw_config.c b/src/mainboard/google/brya/variants/taeko4es/fw_config.c
new file mode 100644
index 0000000000..5068f84581
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/fw_config.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),	/* DMIC_CLK0_R */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),	/* DMIC_DATA0_R */
+
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),	/* I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),	/* I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),	/* I2S_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),	/* I2S_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),	/* I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),	/* I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),	/* I2S_PCH_TX_SPKR_RX_R */
+	PAD_NC(GPP_R7, NONE),			/* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NONE),
+	PAD_NC(GPP_R2, NONE),
+	PAD_NC(GPP_R3, NONE),
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+		printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+		gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+		gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+	}
+
+	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_VS_I2S))) {
+		printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I-VS.\n");
+		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+		gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c
new file mode 100644
index 0000000000..17018cd64d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A6  : ESPI_ALERT1# ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : SRCCLK_OE7# ==> NC */
+	PAD_NC(GPP_A7, NONE),
+	/* A8  : SRCCLKREQ7# ==> NC */
+	PAD_NC(GPP_A8, NONE),
+	/* A12 : SATAXPCIE1 ==> NC */
+	PAD_NC(GPP_A12, NONE),
+	/* A14 : USB_OC1# ==> NC */
+	PAD_NC(GPP_A14, NONE),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC(GPP_A15, NONE),
+	/* A18 : DDSP_HPDB ==> NC */
+	PAD_NC(GPP_A18, NONE),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC(GPP_A22, NONE),
+
+	/* B2  : VRALERT# ==> NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B3  : PROC_GP2 ==> NC */
+	PAD_NC(GPP_B3, NONE),
+	/* B15 : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4 : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+	/* C6  : SML1CLK ==> NC */
+	PAD_NC(GPP_C6, NONE),
+
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC(GPP_D3, NONE),
+	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC(GPP_D9, NONE),
+	/* D10 : ISH_SPI_CLK ==> NC */
+	PAD_NC(GPP_D10, NONE),
+	/* D13 : ISH_UART0_RXD ==> NC */
+	PAD_NC(GPP_D13, NONE),
+	/* D14 : ISH_UART0_TXD ==> NC */
+	PAD_NC(GPP_D14, NONE),
+	/* D15 : ISH_UART0_RTS# ==> NC */
+	PAD_NC(GPP_D15, NONE),
+	/* D16 : ISH_UART0_CTS# ==> NC */
+	PAD_NC(GPP_D16, NONE),
+	/* D17 : UART1_RXD ==> NC */
+	PAD_NC(GPP_D17, NONE),
+
+	/* E0  : SATAXPCIE0 ==> NC */
+	PAD_NC(GPP_E0, NONE),
+	/* E4  : SATA_DEVSLP0 ==> NC */
+	PAD_NC(GPP_E4, NONE),
+	/* E5  : SATA_DEVSLP1 ==> NC */
+	PAD_NC(GPP_E5, NONE),
+	/* E10 : THC0_SPI1_CS# ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* E16 : RSVD_TP ==> NC */
+	PAD_NC(GPP_E16, NONE),
+	/* E17 : THC0_SPI1_INT# ==> NC */
+	PAD_NC(GPP_E17, NONE),
+	/* E18 : DDP1_CTRLCLK ==> NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E19 : DDP1_CTRLDATA ==> NC */
+	PAD_NC(GPP_E19, NONE),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> NC */
+	PAD_NC(GPP_E21, NONE),
+
+	/* F6  : CNV_PA_BLANKING ==> NC */
+	PAD_NC(GPP_F6, NONE),
+	/* F19 : SRCCLKREQ6# ==> NC */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : EXT_PWR_GATE# ==> NC */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
+	/* F22 : VNN_CTRL ==> VNN_CTRL */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	/* F23 : BP105_CTRL ==> PP1050_CTRL */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+	/* H8  : I2C4_SDA ==> NC */
+	PAD_NC(GPP_H8, NONE),
+	/* H9  : I2C4_SCL ==> NC */
+	PAD_NC(GPP_H9, NONE),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	/* H15 : DDPB_CTRLCLK ==> NC */
+	PAD_NC(GPP_H15, NONE),
+	/* H17 : DDPB_CTRLDATA ==> NC */
+	PAD_NC(GPP_H17, NONE),
+	/* H19 : SRCCLKREQ4# ==> NC */
+	PAD_NC(GPP_H19, NONE),
+	/* H21 : IMGCLKOUT2 ==>  NC */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+	/* H23 : SRCCLKREQ5# ==> NC */
+	PAD_NC(GPP_H23, NONE),
+
+	/* R7 : I2S2_RXD ==> NC */
+	PAD_NC(GPP_R7, NONE),
+
+	/* S0 : SNDW0_CLK ==> NC */
+	PAD_NC(GPP_S0, NONE),
+	/* S1 : SNDW0_DATA ==> NC */
+	PAD_NC(GPP_S1, NONE),
+	/* S4 : SNDW2_CLK ==> NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5 : SNDW2_DATA ==> NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+
+	/* GPD11: LANPHYC ==> WWAN_CONFIG1 */
+	PAD_NC(GPD11, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	/*
+	 * B4  : PROC_GP3 ==> SSD_PERST_L
+	 * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
+	 */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/taeko4es/memory.c b/src/mainboard/google/brya/variants/taeko4es/memory.c
new file mode 100644
index 0000000000..9a7ef5c237
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/memory.c
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
+			.dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
+		},
+		.ddr1 = {
+			.dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
+			.dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
+			.dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
+		},
+		.ddr3 = {
+			.dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
+			.dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
+		},
+		.ddr4 = {
+			.dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
+			.dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
+		},
+		.ddr5 = {
+			.dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
+			.dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
+		},
+		.ddr6 = {
+			.dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
+			.dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
+			.dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E11
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E1
+	 * GPIO_MEM_CONFIG_3	GPP_E12
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E11,
+		GPP_E2,
+		GPP_E1,
+		GPP_E12,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_E13 */
+	return gpio_get(GPP_E13);
+}
diff --git a/src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc
new file mode 100644
index 0000000000..2ac3e321b5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267
diff --git a/src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..fda303c037
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt
+
+DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:E       0 (0000)
+K4U6E3S4AA-MGCR                0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E512M32D1NP-046 WT:B       0 (0000)
+K4U6E3S4AB-MGCL                0 (0000)
+H54G46CYRBX267                 0 (0000)
diff --git a/src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..dd80fc82cb
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt
@@ -0,0 +1,6 @@
+MT53E512M32D2NP-046 WT:E
+K4U6E3S4AA-MGCR
+H9HCNNNBKMMLXR-NEE
+MT53E512M32D1NP-046 WT:B
+K4U6E3S4AB-MGCL
+H54G46CYRBX267
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
new file mode 100644
index 0000000000..d485662c67
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -0,0 +1,500 @@
+fw_config
+	field DB_USB 0 1
+		option DB_USB_ABSENT			0
+		option DB_USB3_NO_A			1
+	end
+	field DB_SD 2 3
+		option DB_SD_ABSENT			0
+		option DB_SD_OZ711LV2LN			1
+		option DB_SD_GL9750			2
+		option DB_SD_RTS5232S			3
+	end
+	field KB_BL 4
+		option KB_BL_ABSENT			0
+		option KB_BL_PRESENT			1
+	end
+	field AUDIO 5 7
+		option AUDIO_UNKNOWN			0
+		option AUDIO_MAX98357_ALC5682I_I2S	1
+		option AUDIO_MAX98357_ALC5682I_VS_I2S	2
+	end
+	field KB_LAYOUT 8 9
+		option KB_LAYOUT_DEFAULT		0
+	end
+	field WIFI_SAR_ID 10 11
+		option WIFI_SAR_ID_0			0
+		option WIFI_SAR_ID_1			1
+		option WIFI_SAR_ID_2			2
+		option WIFI_SAR_ID_3			3
+	end
+	field BOOT_NVME_MASK 12
+		option BOOT_NVME_DISABLED		0
+		option BOOT_NVME_ENABLED		1
+	end
+	field BOOT_EMMC_MASK 13
+		option BOOT_EMMC_DISABLED		0
+		option BOOT_EMMC_ENABLED		1
+	end
+	field HPS 17
+		option HPS_ABSENT			0
+		option HPS_PRESENT			1
+	end
+end
+chip soc/intel/alderlake
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
+							FIVR_VOLTAGE_MIN_ACTIVE |
+							FIVR_VOLTAGE_MIN_RETENTION,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
+							FIVR_VOLTAGE_MIN_ACTIVE |
+							FIVR_VOLTAGE_MIN_RETENTION,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1250,
+	}"
+	register "TcssAuxOri" = "1"
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+	register "SaGv" = "SaGv_Enabled"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable Port 1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# DB USB2_C1
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"	# Disable M.2 WWAN
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# Disable M.2 WWAN
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | HPS                       |
+	#| I2C3              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+	# I2C Port Config
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""WWAN""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 74),
+								TEMP_PCT(75, 74),
+								TEMP_PCT(70, 74),
+								TEMP_PCT(65, 74),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_1,
+						.thresholds = {
+								TEMP_PCT(51, 74),
+								TEMP_PCT(47, 60),
+								TEMP_PCT(45, 45),
+								TEMP_PCT(42, 45),
+								TEMP_PCT(37, 35),
+						}
+					},
+					[2] = {
+						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(51, 74),
+								TEMP_PCT(47, 60),
+								TEMP_PCT(45, 45),
+								TEMP_PCT(42, 45),
+								TEMP_PCT(37, 35),
+						}
+					},
+					[3] = {
+						.target = DPTF_TEMP_SENSOR_3,
+						.thresholds = {
+								TEMP_PCT(51, 74),
+								TEMP_PCT(47, 60),
+								TEMP_PCT(45, 45),
+								TEMP_PCT(42, 45),
+								TEMP_PCT(37, 35),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 90, 6000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 90, 6000),
+					[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 90, 6000),
+					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 90, 6000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     100, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     100, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     100, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,     100, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 12000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = { 100, 6000, 220, 2200, },
+					[1] = {  92, 5500, 180, 1800, },
+					[2] = {  85, 5000, 145, 1450, },
+					[3] = {  74, 4620, 115, 1150, },
+					[4] = {  60, 4290,  90,  900, },
+					[5] = {  45, 3980,  55,  550, },
+					[6] = {  35, 3170,  30,  300, },
+					[7] = {  30, 2640,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+			}"
+		end
+		device ref tbt_pcie_rp0 off end
+		device ref tbt_pcie_rp1 off end
+		device ref tbt_pcie_rp2 off end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO AUDIO_MAX98357_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S
+				end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				# Parameter T5 >= 180ms
+				register "generic.reset_delay_ms" = "180"
+				# Parameter T2 >= 1ms
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				# Parameter T1 >= 20ms
+				register "generic.enable_delay_ms" = "20"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
+				# Parameter T4 >= 1ms
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 5d on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/i2c/generic
+				register "hid" = ""GOOG0020""
+				register "desc" = ""Chrome OS HPS""
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"  # EN_HPS_PWR
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)"  # HPS_INT_ODL
+				# HPS uses I2C addresses 0x30 and 0x51.
+				# The address we provide here is not significant because
+				# neither coreboot nor Linux have a driver for HPS,
+				# it's only used from userspace.
+				device i2c 30 on
+					probe HPS HPS_PRESENT
+				end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98357A""
+				register "sdmode_gpio" =
+						"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO AUDIO_MAX98357_ALC5682I_I2S
+					probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S
+				end
+			end
+		end
+		device ref pcie_rp5 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp6 off end
+		device ref pcie_rp8 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+				register "srcclk_pin" = "3"
+				device generic 0 on
+					probe DB_SD DB_SD_OZ711LV2LN
+					probe DB_SD DB_SD_GL9750
+					probe DB_SD DB_SD_RTS5232S
+				end
+			end
+		end
+		device ref pcie_rp9 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				device spi 0 on end
+			end # FPMCU
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "3"
+						register "usb3_port_number" = "3"
+						device generic 2 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref tcss_usb3_port3 on
+							probe DB_USB DB_USB3_NO_A
+						end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port3 on
+							probe DB_USB DB_USB3_NO_A
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb3_port1 on end
+					end
+				end
+			end
+		end
+	end
+end