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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-25 21:23:37 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-28 21:50:12 +0000
commit5b672d595411a50012d3d232db6d886818d44893 (patch)
tree06ead78b90df1ec04fe71c29f52068290821f115 /src/mainboard
parentb0ae42b5bb7fe7c9f6e8301bff8fbabe95294c62 (diff)
soc/amd/common: Access ACPIMMIO via proper symbols
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/inagua/BiosCallOuts.c4
-rw-r--r--src/mainboard/amd/persimmon/BiosCallOuts.c2
-rw-r--r--src/mainboard/amd/south_station/BiosCallOuts.c4
-rw-r--r--src/mainboard/amd/union_station/BiosCallOuts.c4
-rw-r--r--src/mainboard/asrock/e350m1/BiosCallOuts.c2
-rw-r--r--src/mainboard/elmex/pcm205400/BiosCallOuts.c2
-rw-r--r--src/mainboard/google/kahlee/mainboard.c4
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c2
8 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 16058b6d6b..56a7f53706 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -38,7 +38,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
@@ -109,7 +109,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
case 4:
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 1734bc9303..bee2f9eb6b 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -45,7 +45,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
switch (ResetInfo->ResetId)
{
case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index a4438f5fe7..6216a3f0a4 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -38,7 +38,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
@@ -106,7 +106,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
UINT32 GpioMmioAddr;
UINT8 Data8;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
FcnData = Data;
ResetInfo = ConfigPtr;
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index deb6176faf..c324fd6f02 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -38,7 +38,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
@@ -106,7 +106,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
UINT32 GpioMmioAddr;
UINT8 Data8;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
FcnData = Data;
ResetInfo = ConfigPtr;
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index a3d5337894..6bd2f981a8 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -36,7 +36,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
index 1734bc9303..bee2f9eb6b 100644
--- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c
+++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
@@ -45,7 +45,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
switch (ResetInfo->ResetId)
{
case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 239887e167..5e1bdf4c2d 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -134,13 +134,13 @@ static void mainboard_init(void *chip_info)
pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
- clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
+ clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL,
GPP_CLK2_REQ_MAP_MASK,
GPP_CLK2_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */
- clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
+ clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL,
GPP_CLK0_REQ_MAP_MASK,
GPP_CLK0_REQ_MAP_CLK_REQ0 <<
GPP_CLK0_REQ_MAP_SHIFT);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 2129509d55..64ba978ec2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -48,7 +48,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
switch (ResetInfo->ResetId)
{
case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 22:59:04 +0000