- copy_and_run() gets the same calling convention on AMD and on all the others.

- some vx800 Kconfig fixes
- remove warnings...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 16 insertions, 50 deletions

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 576a48e580..593e96cb90 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -102,7 +102,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void sio_init(void)
+static void sio_init(void)
 {
 	u8 reg;
 
diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c
index 49353f7573..fefe553de3 100644
--- a/src/mainboard/digitallogic/msm586seg/mainboard.c
+++ b/src/mainboard/digitallogic/msm586seg/mainboard.c
@@ -7,12 +7,10 @@
 #include "chip.h"
 
 
-static void irqdump()
+static void irqdump(void)
 {
   volatile unsigned char *irq;
   void *mmcr;
-
-
   int i;
   int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
 	        0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
@@ -34,8 +32,9 @@ static void irqdump()
 /* TODO: finish up mmcr struct in sc520.h, and;
    - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
 */
-static void enable_dev(struct device *dev) {
-	volatile struct mmcrpic *pic = MMCRPIC;
+static void enable_dev(struct device *dev)
+{
+	//volatile struct mmcrpic *pic = MMCRPIC;
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
 	/* msm586seg has this register set to a weird value. 
@@ -72,15 +71,11 @@ static void enable_dev(struct device *dev) {
 	mmcr->pic.gp10imap = 0x9;
 	mmcr->pic.gp9imap = 0x4;
 
-
-
-
-
 	irqdump();
 	printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
 
 	printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
-	printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
+	printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
 
 	/* The following block has NOT proven sufficient to get
 	 * the VGA hardware to talk to us 
@@ -124,7 +119,7 @@ static void enable_dev(struct device *dev) {
 	/* still not interrupts. */
 	/* their IRQ table is wrong. Just hardwire it */
 	{
-	  char pciints[4] = {15, 15, 15, 15};
+	  unsigned char pciints[4] = {15, 15, 15, 15};
 	  pci_assign_irqs(0, 12, pciints);
 	}
 	/* the assigned failed but we just noticed -- there is no
@@ -133,6 +128,7 @@ static void enable_dev(struct device *dev) {
 	/* follow fuctory here */
 	mmcr->dmacontrol.extchanmapa = 0x3210;
 }
+
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")
 	.enable_dev = enable_dev
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 7a0d910884..88e8830597 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -146,8 +146,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
 
@@ -175,7 +173,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 	};
 
-        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
+		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index a0ad339cd9..67eda8e8b5 100644
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -44,10 +44,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
 #endif
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -93,9 +89,6 @@ static const struct mem_controller ctrl = {
 
 static void main(unsigned long bist)
 {
-	unsigned long x;
-	device_t dev;
-
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
diff --git a/src/mainboard/via/epia-m700/fadt.c b/src/mainboard/via/epia-m700/fadt.c
index 5a3e3d6997..5802a8ed55 100644
--- a/src/mainboard/via/epia-m700/fadt.c
+++ b/src/mainboard/via/epia-m700/fadt.c
@@ -36,8 +36,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	memcpy(header->asl_compiler_id, "LXB", 8);
 	header->asl_compiler_revision = 0;
 
-	fadt->firmware_ctrl = facs;
-	fadt->dsdt = dsdt;
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
 	fadt->preferred_pm_profile = 0;
 	fadt->sci_int = 0x9;
 
@@ -105,9 +105,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 91ddfee82e..5a81f28517 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -41,7 +41,6 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <string.h>
-#include "cpu/x86/lapic/boot_cpu.c"
 
 /* This file contains the board-special SI value for raminit.c. */
 #include "driving_clk_phase_data.c"
@@ -59,18 +58,6 @@
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
  * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
  */
-void jason_tsc_count_car(void)
-{
-#if 0
-	unsigned long long start;
-	asm volatile ("rdtsc" : "=A" (start));
-	start >>= 20;
-	print_emerg("jason_tsc_count_car=  ");
-	print_emerg_hex32((unsigned long) start);
-	print_emerg("\n");
-#endif
-}
-
 int acpi_is_wakeup_early_via_vx800(void)
 {
 	device_t dev;
@@ -431,8 +418,6 @@ void stage1_main(unsigned long bist)
 	 * g) Rx73h = 32h
 	*/
 
-	jason_tsc_count_car();
-
 	pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
 			   PCI_DEVICE_ID_VIA_VX855_IDE);
 	pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
@@ -462,7 +447,6 @@ void stage1_main(unsigned long bist)
 	 * written, then this must be a CPU restart (result of OS reboot cmd),
 	 * so we need a real "cold boot".
 	 */
-	jason_tsc_count_car();
 	if ((boot_mode != 3)
 	    && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
 		outb(6, 0xcf9);
@@ -471,7 +455,6 @@ void stage1_main(unsigned long bist)
 	/* x86 cold boot I/O cmd. */
 	/* These 2 lines are the same with epia-cn port. */
 	enable_smbus();
-	jason_tsc_count_car();
 
 	/* This fix does help vx800!, but vx855 doesn't need this. */
 	/* smbus_fixup(&ctrl); */
@@ -564,8 +547,6 @@ void stage1_main(unsigned long bist)
 	/* This line is the same with cx700 port. */
 	enable_shadow_ram();
 
-	jason_tsc_count_car();
-
 	/*
 	 * For coreboot most time of S3 resume is the same as normal boot,
 	 * so some memory area under 1M become dirty, so before this happen,
@@ -801,7 +782,6 @@ cpu_reset_x:
 		print_debug("\n");
 #endif
 
-		jason_tsc_count_car();
 		/* Copy and execute coreboot_ram. */
 		copy_and_run(new_cpu_reset);
 		/* We will not return. */
diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c
index a586f0dfde..16277b5faa 100644
--- a/src/mainboard/via/epia-m700/wakeup.c
+++ b/src/mainboard/via/epia-m700/wakeup.c
@@ -111,9 +111,7 @@ static unsigned char show32[6] = {
 
 void acpi_jump_wake(u32 vector)
 {
-	u32 tmp, dwEip;
-	u16 tmpvector;
-	u8 Data;
+	u32 dwEip;
 	struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
 
 	printk(BIOS_DEBUG, "IN ACPI JUMP WAKE TO %x\n", vector);
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index d8bd7608cf..202b117a42 100644
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -75,7 +75,7 @@ static void enable_shadow_ram(void)
 	pci_write_config8(dev, 0x63, shadowreg);
 }
 
-void main(unsigned long bist)
+static void main(unsigned long bist)
 {
 	if (bist == 0) {
 		early_mtrr_init();