diff options
| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2022-01-03 09:23:58 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 14:25:58 +0000 |
| commit | 502a761221ed14c4b381fe33350c9f9d17ec0d76 (patch) | |
| tree | 0657575266fea1d8f0315bd124135bdb45b70b3d /src/mainboard | |
| parent | 6a3ecc508a1946247e56d04413052ff4602cf12f (diff) | |
mb/google/brya/var/vell: Enable SaGv
Enable SaGv support for vell
BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: I01e3da449e2cf53278f625ca265d09f7a1869ef7
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/memory.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c index afbe114f1c..01e0afddd8 100644 --- a/src/mainboard/google/brya/variants/vell/memory.c +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -65,7 +65,8 @@ static const struct mb_cfg baseboard_memcfg = { .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, }, - .ect = true, /* Enable Early Command Training */ + .ect = false, /* Early Command Training */ + .UserBd = BOARD_TYPE_ULT_ULX_T4, .lp5x_config = { .ccc_config = 0xff, diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index fff53b6972..fe929b5fd3 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -32,6 +32,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ |