diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-09-09 12:36:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-10-02 11:52:11 +0000 |
| commit | 4493f66904b1cb4fb33a7d9d08f6f137ebb3c780 (patch) | |
| tree | 9b3f59f00f709166ec25881fd7ba2df434768476 /src/mainboard | |
| parent | a4b7e775663b23f8c7fcbb06e25b3ea196b12662 (diff) | |
mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs
Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index df8bd990ec..0070f22374 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,8 @@ chip soc/intel/cannonlake - # CPU - # Enable Enhanced Intel SpeedStep + # FSP UPDs register "eist_enable" = "true" + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" # Graphics # IGD Displays @@ -14,11 +15,6 @@ chip soc/intel/cannonlake .backlight_pwm_hz = 200, // PWM }" - # FSP Memory - register "enable_c6dram" = "1" - register "SaGv" = "SaGv_Enabled" - - # FSP Silicon # Serial I/O register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |