diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-07-18 22:50:02 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-22 06:41:32 +0000 |
| commit | 4403c384986de98eb51cc6405bb7f5a4ac4b5781 (patch) | |
| tree | 48ccd0ec8069bc25e599be07d76a9b2d797c4bce /src/mainboard | |
| parent | e5e683e84a21dc37f8b4a74e59470dfb4d7a49a2 (diff) | |
mb/google/brya/var/trulo: Add USB2/3 port descriptions
This patch adds descriptions for USB2/3 ports, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime with
port definitions, locations, and type information.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/trulo/overridetree.cb | 63 |
1 files changed, 61 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 9fba6aed2b..56d96ff1c4 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -8,11 +8,70 @@ chip soc/intel/alderlake # S0ix enable register "s0ix_enable" = "1" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB2_A0(MLB) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 (MLB) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB) device domain 0 on device ref igpu on end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end device ref shared_sram on end device ref heci1 on end device ref emmc on end |