diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-01-13 22:53:42 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-14 23:31:53 +0000 |
| commit | 42ea8b2c674ddd9e859a001eac208b8a5da2c0fa (patch) | |
| tree | 5325f9e6657c5bdd513bc9730df035b7d97c742f /src/mainboard | |
| parent | e47c3487056c7ac5d5e967c728f9fb36aaab1b63 (diff) | |
mb/lenovo/x230: Convert remaining PCI numbers into reference names
Change-Id: I38ef315dbdadb140e8e7163e755a078bc906e1b5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/x230/variants/x230/overridetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x230/variants/x230s/overridetree.cb | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index 978d0171f6..487bdfe7a4 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -3,10 +3,10 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - device pci 1c.2 on + device ref pcie_rp3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 (expresscard) - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip ec/lenovo/h8 register "eventa_enable" = "0x01" device pnp ff.2 on end diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 9d020e31ce..e30062ad51 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) register "sata_port_map" = "0x3" - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip ec/lenovo/h8 register "config1" = "0x05" register "config3" = "0xc4" |