diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-11-23 17:04:59 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 10:42:56 +0000 |
| commit | 3e8ca37b6c4b81615138335f323f24ad9d9f1c6c (patch) | |
| tree | 915f02933b36c8b885b4f63217691183d50fa245 /src/mainboard | |
| parent | 8928ae380b7a75b4b23b021b706fa77b3e8d4af5 (diff) | |
mb/google/brya/var/kano: Update thermal table
Update thermal setting from thermal team.
BUG=b:205648035
TEST=build and verified by thermal team.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If5082462b79c88ecf510f7a552381c792604366e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/overridetree.cb | 38 |
1 files changed, 27 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index d7ae3da5e4..56dfc6f9c7 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -59,23 +59,39 @@ chip soc/intel/alderlake .target = DPTF_CPU, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), + TEMP_PCT(75, 80), + TEMP_PCT(68, 70), + TEMP_PCT(62, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(40, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 90), + TEMP_PCT(55, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40), + TEMP_PCT(36, 30), } } }" ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), @@ -83,15 +99,15 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, - .max_power = 15000, + .min_power = 18000, + .max_power = 28000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 55000, - .max_power = 55000, + .min_power = 40000, + .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, |