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authorKangheui Won <khwon@chromium.org>2021-03-23 14:56:31 +1100
committerMartin Roth <martinroth@google.com>2021-03-24 19:37:09 +0000
commit39ef89033624a2d14b0c77cdbdf287dd7d7059e1 (patch)
treecfd0cf17f5f835e7af14a85539f1fcf3ab4ce506 /src/mainboard
parent6d837df90838bfb3a9c877b5c0b2eeda85e3d9f0 (diff)
mb/google/guybrush: disable KBRSTEN
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/guybrush/mainboard.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 72ad7a8a0f..ffa682218d 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -1,9 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <soc/acpi.h>
+#include <soc/southbridge.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -88,6 +90,16 @@ static void mainboard_configure_gpios(void)
{
size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios;
+ u32 reg;
+
+ /*
+ * Disable KBRST feature
+ * KBRSTEN is set to 1 on reset and this causes system reset
+ * if GPIO 129 is configured as GPO_LOW.
+ * */
+ reg = pm_read8(PM_RST_CTRL1);
+ reg &= ~KBRSTEN;
+ pm_write8(PM_RST_CTRL1, reg);
base_gpios = variant_base_gpio_table(&base_num_gpios);
override_gpios = variant_override_gpio_table(&override_num_gpios);