diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-08-11 10:55:08 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-27 02:50:31 +0000 |
| commit | 3412d28b454202a945cbac140677a29753cfcc5b (patch) | |
| tree | 7f161c7f2b535dc4d62a477cadce14a32fabe06e /src/mainboard | |
| parent | d59c950379e54d9c0a42fddeac38a2108c5ee953 (diff) | |
mb/google/dedede/variant/drawcia: Include SPD for MT53E512M32D1NP-046 WT:B
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B.
This part is already in global_lp4x_mem_parts.json.txt, and use
/util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs.
BUG=b:196951879
BRANCH=firmware-dedede-13606.B
TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage
Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
3 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc index f6282bf04c..a934428471 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt index 856d016914..e8ec694d26 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt @@ -2,3 +2,4 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt index 26c06b6f40..09ed38129d 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt @@ -1,3 +1,4 @@ MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR +MT53E512M32D1NP-046 WT:B |