diff options
| author | huang lin <hl@rock-chips.com> | 2014-10-16 09:27:31 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-08 09:28:43 +0200 |
| commit | 2d3d452d521db352b9f9a978314a997d3dee5bd6 (patch) | |
| tree | acd43f107534651504e130310cec7b00fd7c9b31 /src/mainboard | |
| parent | 6f9feb4ffb2ca58478265a3f111066cd53cf73ed (diff) | |
rk3288: configure l2ctlr in romstage
Data RAM write latency: 2 cycles
Data RAM read latency: 2 cycles
Data RAM setup latency: 1 cycle
Tag RAM write latency: 1 cycle
Tag RAM read latency: 1 cycle
Tag RAM setup latency: 1 cycle
BUG=None
TEST=Boot Veyron Pinky
Change-Id: I1d710f65114be6a976aa3fe23b076e89c14ac8b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 421c2e5ba44f1693f8b3c869289fc93ab9ef5965
Original-Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223713
Original-Reviewed-by: Doug Anderson <dianders@chromium.org>
Original-Commit-Queue: Doug Anderson <dianders@chromium.org>
Reviewed-on: http://review.coreboot.org/9347
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/veyron_pinky/romstage.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 6f9b9d1392..76a57e2c77 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -55,6 +55,25 @@ static void regulate_vdd_log(unsigned int mv) pwm_init(1, period_ns, duty_ns); } +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + void main(void) { #if CONFIG_COLLECT_TIMESTAMPS @@ -66,6 +85,7 @@ void main(void) #endif console_init(); + configure_l2ctlr(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); |