mainboard/google/cheza: Add support for Cheza

TEST=build

Change-Id: I32d185741ce20a3a82e6895de3026ade52d0bcc8
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

11 files changed, 257 insertions, 0 deletions

diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig
new file mode 100644
index 0000000000..b60c1b0c86
--- /dev/null
+++ b/src/mainboard/google/cheza/Kconfig
@@ -0,0 +1,41 @@
+
+config BOARD_GOOGLE_CHEZA_COMMON  # Umbrella option to be selected by variants
+	def_bool n
+
+if BOARD_GOOGLE_CHEZA_COMMON
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select COMMON_CBFS_SPI_WRAPPER
+	select SOC_QUALCOMM_SDM845
+	select SPI_FLASH
+	select MAINBOARD_HAS_CHROMEOS
+
+config VBOOT
+	select VBOOT_VBNV_FLASH
+	select VBOOT_MOCK_SECDATA
+	select VBOOT_NO_BOARD_SUPPORT
+
+config MAINBOARD_DIR
+	string
+	default google/cheza
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+##########################################################
+#### Update below when adding a new derivative board. ####
+##########################################################
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Cheza" if BOARD_GOOGLE_CHEZA
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "CHEZA TEST 1859" if BOARD_GOOGLE_CHEZA
+
+endif # BOARD_GOOGLE_CHEZA_COMMON
diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name
new file mode 100644
index 0000000000..fbfe4c919b
--- /dev/null
+++ b/src/mainboard/google/cheza/Kconfig.name
@@ -0,0 +1,4 @@
+
+config BOARD_GOOGLE_CHEZA
+	bool "Cheza"
+	select BOARD_GOOGLE_CHEZA_COMMON
diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc
new file mode 100644
index 0000000000..0e2f6bddb0
--- /dev/null
+++ b/src/mainboard/google/cheza/Makefile.inc
@@ -0,0 +1,15 @@
+
+bootblock-y += memlayout.ld
+bootblock-y += chromeos.c
+bootblock-y += bootblock.c
+
+verstage-y += memlayout.ld
+verstage-y += chromeos.c
+
+romstage-y += memlayout.ld
+romstage-y += chromeos.c
+romstage-y += romstage.c
+
+ramstage-y += memlayout.ld
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/cheza/board_info.txt
new file mode 100644
index 0000000000..5e6e3b235a
--- /dev/null
+++ b/src/mainboard/google/cheza/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Cheza Qualcomm SDM845 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c
new file mode 100644
index 0000000000..6718d52156
--- /dev/null
+++ b/src/mainboard/google/cheza/bootblock.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <timestamp.h>
+
+void bootblock_mainboard_init(void)
+{
+
+}
diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c
new file mode 100644
index 0000000000..538e46fa4b
--- /dev/null
+++ b/src/mainboard/google/cheza/chromeos.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+
+}
diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd
new file mode 100644
index 0000000000..29f16326ac
--- /dev/null
+++ b/src/mainboard/google/cheza/chromeos.fmd
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 and
+## only version 2 as published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+FLASH@0x0 0x800000 {
+	WP_RO@0x0 0x300000 {
+		RO_SECTION@0x0 0x2E0000 {
+			BOOTBLOCK@0 128K
+			COREBOOT(CBFS)@0x20000 0x1E0000
+			FMAP@0x200000 0x1000
+			GBB@0x201000 0xDEF00
+			RO_FRID@0x2DFF00 0x100
+		}
+		RO_VPD@0x2E0000 0x2000
+	}
+
+	RW_NVRAM@0x300000 0x8000
+	RW_ELOG@0x308000 0x8000
+	RW_VPD@0x310000 0x8000
+	RW_CDT@0x318000 0x8000
+
+	RW_SECTION_A@0x320000 0x268000 {
+		VBLOCK_A@0x0 0x2000
+		FW_MAIN_A(CBFS)@0x2000 0x1E1F00
+		RW_FWID_A@0x1E3F00 0x100
+		RW_DDR_TRAINING_A@0x1E4000 0x4000
+		RW_XBL_BUFFER_A@0x1E8000 0x4000
+	}
+
+	RW_SHARED@0x588000 0x10000 {
+		SHARED_DATA@0x0 0x10000
+	}
+
+	RW_SECTION_B@0x598000 0x268000 {
+		VBLOCK_B@0x0 0x2000
+		FW_MAIN_B(CBFS)@0x2000 0x1E1F00
+		RW_FWID_B@0x1E3F00 0x100
+		RW_DDR_TRAINING_B@0x1E4000 0x4000
+		RW_XBL_BUFFER_B@0x1E8000 0x4000
+	}
+}
diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb
new file mode 100644
index 0000000000..1116cca15c
--- /dev/null
+++ b/src/mainboard/google/cheza/devicetree.cb
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 and
+## only version 2 as published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/qualcomm/sdm845
+	device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c
new file mode 100644
index 0000000000..c249a32456
--- /dev/null
+++ b/src/mainboard/google/cheza/mainboard.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <bootblock_common.h>
+#include <timestamp.h>
+
+static void mainboard_init(device_t dev)
+{
+
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.name = CONFIG_MAINBOARD_PART_NUMBER,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld
new file mode 100644
index 0000000000..cbc50e2d11
--- /dev/null
+++ b/src/mainboard/google/cheza/memlayout.ld
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+ #include <soc/memlayout.ld>
diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c
new file mode 100644
index 0000000000..c930016080
--- /dev/null
+++ b/src/mainboard/google/cheza/romstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <cbmem.h>
+#include <halt.h>
+#include <program_loading.h>
+#include <console/console.h>
+#include <timestamp.h>
+
+void main(void)
+{
+	console_init();
+	exception_init();
+	cbmem_initialize_empty();
+	run_ramstage();
+}