diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 19:16:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-13 08:24:29 +0000 |
| commit | 2b4da16ea410c7536ec7cb9f600877ec5ae8e502 (patch) | |
| tree | 9b898b602aa2ab44df08d730da48b1c0b7e19377 /src/mainboard | |
| parent | 7f7c3882a6ac776ba215551a3c5cd9a7379933b5 (diff) | |
mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting
With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.
Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/hp/280_g2/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/hp/280_g2/romstage.c b/src/mainboard/hp/280_g2/romstage.c index 8f32d2495a..9b3d385b42 100644 --- a/src/mainboard/hp/280_g2/romstage.c +++ b/src/mainboard/hp/280_g2/romstage.c @@ -23,8 +23,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) get_spd_smbus(&blk); + mem_cfg->CaVrefConfig = 2; mem_cfg->DqPinsInterleaved = true; - mem_cfg->UserBd = BOARD_TYPE_DESKTOP; mem_cfg->MemorySpdDataLen = blk.len; |