diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-06-06 11:41:08 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-06-07 11:15:00 +0000 |
| commit | 2993553de6cc849a938e7ccaba5bb929ea36a804 (patch) | |
| tree | b8d4874744fbce44aedb1896e749845bcdd754e4 /src/mainboard | |
| parent | ca9f94854176808651d075b968aa7551cf4d2ae6 (diff) | |
soc/intel/common/uart: Drop chip in favor of devicetree ops
It is now possible to hook up device ops directly to devices in
devicetree which removes the need for a fake chip.
This also fixes Hermes booting as the PCI ops were incorrectly hooked up
to a dummy device. The intel uart driver was requesting a resource from
the generic device and died since it does not exist:
[EMERG] GENERIC: 0.0 missing resource: 10
This was broken in commit b9165199c32a (mb/prodrive/hermes: Rework UART
devicetree entry).
Change-Id: I3b32d1cc52afaed2a321eea5815f2957fe730f79
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82940
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index ea9f6731f7..ee73800c40 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -170,12 +170,7 @@ chip soc/intel/cannonlake # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. device ref i2c4 hidden end - device ref uart2 hidden # in ACPI mode - chip soc/intel/common/block/uart - register "devid" = "PCI_DID_INTEL_CNP_H_UART2" - device generic 0 hidden end - end - end + device ref uart2 hidden end # in ACPI mode device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "1" |