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authorSean Rhodes <sean@starlabs.systems>2022-05-16 08:28:23 +0100
committerMartin L Roth <gaumless@tutanota.com>2022-05-28 14:47:56 +0000
commit284c8e7f20e697a60f20468b28b5d60c308aecfe (patch)
tree92068d113f96b6355d155b5de6c1c19822a9d917 /src/mainboard
parent8f5a4d372ef064811be12cd75cba5f6b76bd61cf (diff)
mb/starlabs/lite/glk: Remove unnecessary DPTF UPD
The default for DPTF is off (0), so remove the entry that sets this to off. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/starlabs/lite/variants/glk/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
index aef0a7f7bc..287a64e0ae 100644
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@@ -20,8 +20,6 @@ chip soc/intel/apollolake
LPC_IOE_EC_62_66 |
LPC_IOE_KBC_60_64"
- register "dptf_enable" = "0"
-
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"