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authorAngel Pons <th3fanbus@gmail.com>2023-01-12 15:52:55 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-01-13 17:17:24 +0000
commit1cb930b5d181b1e15275e45de887e05f096dbc85 (patch)
treefe7d2bbd30ccddc74f812507e99cece10e6a1f04 /src/mainboard
parent9ed576fbcd919b12c0592a0111a28f9142367a1d (diff)
mb/lenovo/t520: Disable SATA2 and Thermal on W520
If a discoverable device (e.g. a PCI device) does not appear in the devicetree (typically because it is removable), coreboot enables it by default. Disable the SATA2 (device for SATA ports 4 and 5, which is not used in AHCI mode) and Thermal devices on W520 as well. Both devices were only disabled on the T520. Tested, this change fixes a long boot time when using MrChromebox's edk2 payload on the W520, likely related to the following errors: AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 0 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 1 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 2 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 3 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 4 Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/lenovo/t520/devicetree.cb2
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/overridetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 5048c698d7..55c8d981fd 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -145,6 +145,8 @@ chip northbridge/intel/sandybridge
device i2c 5f on end
end
end # SMBus
+ device pci 1f.5 off end # IDE controller
+ device pci 1f.6 off end # Thermal controller
end
end
end
diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
index 407e02d907..b976d6d904 100644
--- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
@@ -9,8 +9,6 @@ chip northbridge/intel/sandybridge
register "wwan_gpio_lvl" = "0"
end
end # LPC bridge
- device pci 1f.5 off end # IDE controller
- device pci 1f.6 off end # Thermal controller
end
end
end