diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2005-11-24 02:45:45 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2005-11-24 02:45:45 +0000 |
| commit | 164586bad8abe494a765f4ab11740855916f4706 (patch) | |
| tree | 8cf12220d8865e69c9d0e8a0b02a3216587f6af7 /src/mainboard | |
| parent | ee5ee894b81860e54d77d43eba512022e379def4 (diff) | |
adding support for serengeti leopard
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
31 files changed, 6181 insertions, 0 deletions
diff --git a/src/mainboard/amd/serengeti_leopard/Config.lb b/src/mainboard/amd/serengeti_leopard/Config.lb new file mode 100644 index 0000000000..aea3dec107 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/Config.lb @@ -0,0 +1,345 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/si/3114 + +#needed by irq_tables and mptable and acpi_tables +object get_bus_conf.o + +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + object dsdt.o + object ssdt.o + if ACPI_SSDTX_NUM + object ssdt2.o + # object ssdt3.o + # object ssdt4.o + # object ssdt5.o + # object ssdt6.o + # object ssdt7.o + # object ssdt8.o + end +end + +object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +end +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +if USE_DCACHE_RAM +else +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc +end + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +end + +## +## Include the secondary Configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + +# sample config for amd/serengeti_leopard +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + diff --git a/src/mainboard/amd/serengeti_leopard/Options.lb b/src/mainboard/amd/serengeti_leopard/Options.lb new file mode 100644 index 0000000000..a2bf814ebd --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/Options.lb @@ -0,0 +1,252 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses HAVE_ACPI_TABLES +uses ACPI_SSDTX_NUM +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses _RAMBASE +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses K8_E0_MEM_HOLE_SIZEK + +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses CONFIG_USE_INIT + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=524288 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +default FALLBACK_SIZE=131072 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## ACPI tables will be included +default HAVE_ACPI_TABLES=1 +## extra SSDT num +default ACPI_SSDTX_NUM=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + +#1G memory hole +default K8_E0_MEM_HOLE_SIZEK=0x100000 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="serengeti_leopard" +default MAINBOARD_VENDOR="AMD" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +### End Options.lb +end diff --git a/src/mainboard/amd/serengeti_leopard/acpi_tables.c b/src/mainboard/amd/serengeti_leopard/acpi_tables.c new file mode 100644 index 0000000000..bafc6ad667 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/acpi_tables.c @@ -0,0 +1,355 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +/* + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#define DUMP_ACPI_TABLES 1 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(unsigned start, unsigned end) +{ + + unsigned i; + print_debug("dump_mem:"); + for(i=start;i<end;i++) { + if((i & 0xf)==0) { + printk_debug("\n%08x:", i); + } + printk_debug(" %02x", (unsigned char)*((unsigned char *)i)); + } + print_debug("\n"); + } +#endif + +#define HC_POSSIBLE_NUM 8 +extern unsigned char AmlCode[]; +extern unsigned char AmlCode_ssdt[]; + +#if ACPI_SSDTX_NUM >= 1 +extern unsigned char AmlCode_ssdt2[]; +//extern unsigned char AmlCode_ssdt3[]; +//extern unsigned char AmlCode_ssdt4[]; +//extern unsigned char AmlCode_ssdt5[]; +//extern unsigned char AmlCode_ssdt6[]; +//extern unsigned char AmlCode_ssdt7[]; +//extern unsigned char AmlCode_ssdt8[]; +#endif + +#define IO_APIC_ADDR 0xfec00000UL + +extern unsigned char bus_isa; +extern unsigned char bus_8132_0; +extern unsigned char bus_8132_1; +extern unsigned char bus_8132_2; +extern unsigned char bus_8111_0; +extern unsigned char bus_8111_1; +extern unsigned char bus_8151_0; +extern unsigned char bus_8151_1; +extern unsigned apicid_8111; +extern unsigned apicid_8132_1; +extern unsigned apicid_8132_2; + +extern unsigned pci1234[]; +extern unsigned hc_possible_num; +extern unsigned sblk; +extern unsigned sbdn; + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base=0x18; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write 8111 IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, apicid_8111, + IO_APIC_ADDR, 0); + + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, apicid_8132_1, + res->base, gsi_base ); + gsi_base+=7; + + } + } + dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, apicid_8132_2, + res->base, gsi_base ); + gsi_base+=7; + } + } + } + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 0, 0, 2, 5 ); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high*/ + + + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* 1: LINT1 connect to NMI */ + + + return current; +} + +//FIXME: next could be moved to northbridge/amd/amdk8/amdk8_acpi.c or cpu/amd/k8/k8_acpi.c begin +static void int_to_stream(uint32_t val, uint8_t *dest) +{ + int i; + for(i=0;i<4;i++) { + *(dest+i) = (val >> (8*i)) & 0xff; + } +} + +extern void get_bus_conf(void); + +static void update_ssdt(void *ssdt) +{ + uint8_t *BUSN; + uint8_t *MMIO; + uint8_t *PCIO; + uint8_t *SBLK; + uint8_t *TOM1; + uint8_t *HCLK; + uint8_t *SBDN; + int i; + device_t dev; + uint32_t dword; + msr_t msr; + + BUSN = ssdt+0x3a; //+5 will be next BUSN + MMIO = ssdt+0x57; //+5 will be next MMIO + PCIO = ssdt+0xaf; //+5 will be next PCIO + SBLK = ssdt+0xdc; // one byte + TOM1 = ssdt+0xe3; // + HCLK = ssdt+0xfa; //+5 will be next HCLK + SBDN = ssdt+0xed;// + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + for(i=0;i<4;i++) { + dword = pci_read_config32(dev, 0xe0+i*4); + int_to_stream(dword, BUSN+i*5); + } + + for(i=0;i<0x10;i++) { + dword = pci_read_config32(dev, 0x80+i*4); + int_to_stream(dword, MMIO+i*5); + } + + for(i=0;i<0x08;i++) { + dword = pci_read_config32(dev, 0xc0+i*4); + int_to_stream(dword, PCIO+i*5); + } + + get_bus_conf(); //it will get sblk, pci1234, and sbdn + + *SBLK = (uint8_t)(sblk); + + msr = rdmsr(TOP_MEM); + int_to_stream(msr.lo, TOM1); + + for(i=0;i<hc_possible_num;i++) { + int_to_stream(pci1234[i], HCLK + i*5); + } + for(i=hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + int_to_stream(0x00000000, HCLK + i*5); + } + + int_to_stream(sbdn, SBDN); + +} +//end + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdtx; + + unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM]; + + int i; + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt,hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + acpi_add_table(rsdt,madt); + + /* SRAT */ + printk_debug("ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current+=srat->header.length; + acpi_add_table(rsdt,srat); + + /* SSDT */ + printk_debug("ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode_ssdt)->length; + memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length); + //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c + update_ssdt((void*)ssdt); + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + acpi_add_table(rsdt,ssdt); + +#if ACPI_SSDTX_NUM >= 1 + // we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1] + AmlCode_ssdtx[1] = AmlCode_ssdt2; +// AmlCode_ssdtx[2] = AmlCode_ssdt3; +// AmlCode_ssdtx[3] = AmlCode_ssdt4; +// AmlCode_ssdtx[4] = AmlCode_ssdt5; +// AmlCode_ssdtx[5] = AmlCode_ssdt6; +// AmlCode_ssdtx[6] = AmlCode_ssdt7; +// AmlCode_ssdtx[7] = AmlCode_ssdt8; + + //same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table + + for(i=1;i<hc_possible_num;i++) { // 0: is hc sblink + if((pci1234[i] & 1) != 1 ) continue; + printk_debug("ACPI: * SSDT for PCI%d\n", i+1); //pci0 and pci1 are in dsdt + ssdtx = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode_ssdtx[i])->length; + memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length); + acpi_add_table(rsdt,ssdtx); + } +#endif + + + /* FACS */ + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk_debug("ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode)->length; + memcpy((void *)dsdt,(void *)AmlCode, \ + ((acpi_header_t *)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + + /* FDAT */ + printk_debug("ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdt,fadt); + +#if DUMP_ACPI_TABLES == 1 + printk_debug("rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk_debug("rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk_debug("madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk_debug("srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk_debug("ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk_debug("fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk_info("ACPI: done.\n"); + return current; +} + diff --git a/src/mainboard/amd/serengeti_leopard/auto.c b/src/mainboard/amd/serengeti_leopard/auto.c new file mode 100644 index 0000000000..c152669175 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/auto.c @@ -0,0 +1,360 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/cpu_rev.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + +static void hard_reset(void) +{ + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + + set_bios_reset(); + + /* enable cf9 */ + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); +} + +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + } + else { + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + } + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); + } +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +#define SMBUS_HUB 0x18 + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); +} +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_HUB 0x18 + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); +} +#endif + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +//#include "northbridge/amd/amdk8/setup_resource_map.c" +#define K8_4RANK_DIMM_SUPPORT 1 +#include "northbridge/amd/amdk8/raminit.c" + +#if 0 + #define ENABLE_APIC_EXT_ID 1 + #define APIC_ID_OFFSET 0x10 + #define LIFT_BSP_APIC_ID 0 +#else + #define ENABLE_APIC_EXT_ID 0 +#endif +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + +/* tyan does not want the default */ +#include "resourcemap.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) + +#define RC0 ((1<<0)<<8) +#define RC1 ((1<<1)<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +static void main(unsigned long bist) +{ + static const struct mem_controller cpu[] = { +#if FIRST_CPU + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { RC0|DIMM0, 0, 0, 0 }, + .channel1 = { RC0|DIMM1, 0, 0, 0 }, + }, +#endif +#if SECOND_CPU + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { RC1|DIMM0, 0 , 0, 0 }, + .channel1 = { RC1|DIMM1, 0 , 0, 0 }, + + }, +#endif + + }; + + int needs_reset; +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + amd_early_mtrr_init(); + +#if CONFIG_LOGICAL_CPUS==1 + set_apicid_cpuid_lo(); + + id = get_node_core_id_x(); // that is initid + #if ENABLE_APIC_EXT_ID == 1 + if(id.coreid == 0) { + enable_apic_ext_id(id.nodeid); + } + #endif +#else + nodeid = get_node_id(); + #if ENABLE_APIC_EXT_ID == 1 + enable_apic_ext_id(nodeid); + #endif +#endif + + enable_lapic(); + init_timer(); + +#if CONFIG_LOGICAL_CPUS==1 + #if ENABLE_APIC_EXT_ID == 1 + #if LIFT_BSP_APIC_ID == 0 + if( id.nodeid != 0 ) //all except cores in node0 + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); + #endif + + if(id.coreid == 0) { + if (cpu_init_detected(id.nodeid)) { + asm volatile ("jmp __cpu_reset"); + } + distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); + } + +#else + #if ENABLE_APIC_EXT_ID == 1 + #if LIFT_BSP_APIC_ID == 0 + if(nodeid != 0) + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 + + #endif + + if (cpu_init_detected(nodeid)) { + asm volatile ("jmp __cpu_reset"); + } + distinguish_cpu_resets(nodeid); +#endif + + if (!boot_cpu() +#if CONFIG_LOGICAL_CPUS==1 + || (id.coreid != 0) +#endif + ) { + stop_this_cpu(); // it will stop all cores except core0 of cpu0 + } + } + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_serengeti_leopard_resource_map(); + needs_reset = setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); +#endif + +#if 0 + // You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec + needs_reset |= ht_setup_chains(2); +#else + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x(); +#endif + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + +#if 0 + dump_pci_devices(); +#endif + + /* Check all of memory */ +#if 0 + msr_t msr; + msr = rdmsr(TOP_MEM2); + print_debug("TOP_MEM2: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); +#endif + +#if 0 + ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#endif + +#if 0 + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x00100000); + // Check 16MB of memory @ 2GB + ram_check(0x80000000, 0x80100000); +#endif + + +} diff --git a/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c new file mode 100644 index 0000000000..6981b2f52d --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c @@ -0,0 +1,579 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +#define ASSEMBLY 1 +#define __ROMCC__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" + +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + +#include "northbridge/amd/amdk8/cpu_rev.c" +#define K8_HT_FREQ_1G_SUPPORT 0 +#define K8_SCAN_PCI_BUS 0 +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +/* Look up a which bus a given node/link combination is on. + * return 0 when we can't find the answer. + */ +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + +static void hard_reset(void) +{ + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); + + set_bios_reset(); + + /* enable cf9 */ + pci_write_config8(dev, 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + device_t dev; + + /* Find the device */ + dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); + + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); +} + +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + } + else { + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + } + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); + } +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +#define SMBUS_HUB 0x18 + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); +} +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_HUB 0x18 + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); +} +#endif + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define K8_4RANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/raminit.c" +#if 0 + #define ENABLE_APIC_EXT_ID 1 + #define APIC_ID_OFFSET 0x10 + #define LIFT_BSP_APIC_ID 0 +#else + #define ENABLE_APIC_EXT_ID 0 +#endif +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + + /* tyan does not want the default */ +#include "resourcemap.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) + +#define RC0 ((1<<0)<<8) +#define RC1 ((1<<1)<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +#include "cpu/amd/car/copy_and_run.c" + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void real_main(unsigned long bist); + +void amd64_main(unsigned long bist) +{ +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + /* Make cerain my local apic is useable */ +// enable_lapic(); + +#if CONFIG_LOGICAL_CPUS==1 + id = get_node_core_id_x(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(id.nodeid)) { +#else +// nodeid = lapicid(); + nodeid = get_node_id(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(nodeid)) { +#endif + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* Is this a secondary cpu? */ +// post_code(0x21); + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the ck804 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ +// post_code(0x22); + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: +// post_code(0x23); + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + ); + cpu_reset: +// post_code(0x24); +#if 0 + //CPU reset will reset memtroller ??? + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + ); +#endif + + fallback_image: +// post_code(0x25); + real_main(bist); +} +void real_main(unsigned long bist) +#else +void amd64_main(unsigned long bist) +#endif +{ + static const struct mem_controller cpu[] = { +#if FIRST_CPU + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { RC0|DIMM0, 0, 0, 0 }, + .channel1 = { RC0|DIMM1, 0, 0, 0 }, + }, +#endif +#if SECOND_CPU + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { RC1|DIMM0, 0 , 0, 0 }, + .channel1 = { RC1|DIMM1, 0 , 0, 0 }, + + }, +#endif + + }; + + int needs_reset; + unsigned cpu_reset = 0; + + if (bist == 0) { +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + /* Skip this if there was a built in self test failure */ +// amd_early_mtrr_init(); # don't need, already done in cache_as_ram + +#if CONFIG_LOGICAL_CPUS==1 + set_apicid_cpuid_lo(); + id = get_node_core_id_x(); // that is initid + #if ENABLE_APIC_EXT_ID == 1 + if(id.coreid == 0) { + enable_apic_ext_id(id.nodeid); + } + #endif +#else + nodeid = get_node_id(); + #if ENABLE_APIC_EXT_ID == 1 + enable_apic_ext_id(nodeid); + #endif +#endif + + enable_lapic(); + init_timer(); + +// post_code(0x30); + +#if CONFIG_LOGICAL_CPUS==1 + #if (ENABLE_APIC_EXT_ID == 1) + #if LIFT_BSP_APIC_ID == 0 + if( id.nodeid != 0 ) //all except cores in node0 + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); + #endif + if(id.coreid == 0) { + if (cpu_init_detected(id.nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); + cpu_reset = 1; + goto cpu_reset_x; + } + distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); + } +#else + #if (ENABLE_APIC_EXT_ID == 1) + #if LIFT_BSP_APIC_ID == 0 + if(nodeid != 0) + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 + + #endif + if (cpu_init_detected(nodeid)) { +// __asm__ volatile ("jmp __cpu_reset"); + cpu_reset = 1; + goto cpu_reset_x; + } + distinguish_cpu_resets(nodeid); +#endif + +// post_code(0x31); + + if (!boot_cpu() +#if CONFIG_LOGICAL_CPUS==1 + || (id.coreid != 0) +#endif + ) { + // We need stop the CACHE as RAM for this CPU too + #include "cpu/amd/car/cache_as_ram_post.c" + stop_this_cpu(); // it will stop all cores except core0 of cpu0 + } + } + +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_serengeti_leopard_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + needs_reset = setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); +#endif +#if 0 + + // You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec + needs_reset |= ht_setup_chains(2); +#else + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x(); +#endif + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif +#if 0 + dump_smbus_registers(); +#endif + + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + +#if 0 + print_pci_devices(); +#endif + +#if 0 + dump_pci_devices(); +#endif + + /* Check all of memory */ +#if 0 + msr_t msr; + msr = rdmsr(TOP_MEM2); + print_debug("TOP_MEM2: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); +#endif +#if 0 + ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#endif + +#if 0 + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x00100000); + // Check 16MB of memory @ 2GB + ram_check(0x80000000, 0x80100000); +#endif + +#if 1 + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); +#if CONFIG_USE_INIT + printk_debug("v_esp=%08x\r\n", v_esp); +#else + print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); +#endif + } +#endif + +#if 1 + + +cpu_reset_x: + +#if CONFIG_USE_INIT + printk_debug("cpu_reset = %08x\r\n",cpu_reset); +#else + print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); +#endif + + if(cpu_reset == 0) { + print_debug("Clearing initial memory region: "); + } + print_debug("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cpu/amd/car/cache_as_ram_post.c" + } + else { +#undef CLEAR_FIRST_1M_RAM +#include "cpu/amd/car/cache_as_ram_post.c" + } + + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/ + if(new_cpu_reset==0) { + print_debug("done\r\n"); + } else + { + print_debug("\r\n"); + } + +#if CONFIG_USE_INIT + printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset); +#else + print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); +#endif + /*copy and execute linuxbios_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } +#endif + + + print_debug("should not be here -\r\n"); + +} diff --git a/src/mainboard/amd/serengeti_leopard/chip.h b/src/mainboard/amd/serengeti_leopard/chip.h new file mode 100644 index 0000000000..e84ffdf729 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/chip.h @@ -0,0 +1,6 @@ +extern struct chip_operations mainboard_amd_serengeti_leopard_ops; + +struct mainboard_amd_serengeti_leopard_config { +// int fixup_scsi; +// int fixup_vga; +}; diff --git a/src/mainboard/amd/serengeti_leopard/cmos.layout b/src/mainboard/amd/serengeti_leopard/cmos.layout new file mode 100644 index 0000000000..c1f3d75316 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/serengeti_leopard/dsdt.c b/src/mainboard/amd/serengeti_leopard/dsdt.c new file mode 100644 index 0000000000..01c179104d --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dsdt.c @@ -0,0 +1,837 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +/* + * Compilation of "dsdt_lb.dsl" - Sat Sep 17 23:29:24 2005 + * + */ +unsigned char AmlCode[] = +{ + 0x44,0x53,0x44,0x54,0xD7,0x18,0x00,0x00, /* 00000000 "DSDT...." */ + 0x01,0xF4,0x41,0x4D,0x44,0x2D,0x4B,0x38, /* 00000008 "..AMD-K8" */ + 0x41,0x4D,0x44,0x41,0x43,0x50,0x49,0x00, /* 00000010 "AMDACPI." */ + 0x00,0x00,0x04,0x06,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ + 0x09,0x03,0x05,0x20,0x10,0x39,0x5F,0x50, /* 00000020 "... .9_P" */ + 0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */ + 0x30,0x00,0x10,0xC0,0x00,0x00,0x06,0x5B, /* 00000030 "0......[" */ + 0x83,0x0B,0x43,0x50,0x55,0x31,0x01,0x00, /* 00000038 "..CPU1.." */ + 0x00,0x00,0x00,0x00,0x5B,0x83,0x0B,0x43, /* 00000040 "....[..C" */ + 0x50,0x55,0x32,0x02,0x00,0x00,0x00,0x00, /* 00000048 "PU2....." */ + 0x00,0x5B,0x83,0x0B,0x43,0x50,0x55,0x33, /* 00000050 ".[..CPU3" */ + 0x03,0x00,0x00,0x00,0x00,0x00,0x14,0x06, /* 00000058 "........" */ + 0x46,0x57,0x53,0x4F,0x00,0x08,0x5F,0x53, /* 00000060 "FWSO.._S" */ + 0x30,0x5F,0x12,0x06,0x04,0x00,0x00,0x00, /* 00000068 "0_......" */ + 0x00,0x08,0x5F,0x53,0x31,0x5F,0x12,0x06, /* 00000070 ".._S1_.." */ + 0x04,0x01,0x01,0x01,0x01,0x08,0x5F,0x53, /* 00000078 "......_S" */ + 0x33,0x5F,0x12,0x0A,0x04,0x0A,0x05,0x0A, /* 00000080 "3_......" */ + 0x05,0x0A,0x05,0x0A,0x05,0x08,0x5F,0x53, /* 00000088 "......_S" */ + 0x35,0x5F,0x12,0x0A,0x04,0x0A,0x07,0x0A, /* 00000090 "5_......" */ + 0x07,0x0A,0x07,0x0A,0x07,0x10,0x82,0x1C, /* 00000098 "........" */ + 0x01,0x5F,0x53,0x42,0x5F,0x5B,0x82,0x3E, /* 000000A0 "._SB_[.>" */ + 0x50,0x43,0x49,0x30,0x08,0x5F,0x48,0x49, /* 000000A8 "PCI0._HI" */ + 0x44,0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F, /* 000000B0 "D.A...._" */ + 0x41,0x44,0x52,0x0C,0x00,0x00,0x18,0x00, /* 000000B8 "ADR....." */ + 0x08,0x5F,0x55,0x49,0x44,0x01,0x08,0x5F, /* 000000C0 "._UID.._" */ + 0x42,0x42,0x4E,0x00,0x5B,0x80,0x4C,0x44, /* 000000C8 "BBN.[.LD" */ + 0x54,0x31,0x02,0x0A,0xA4,0x01,0x5B,0x81, /* 000000D0 "T1....[." */ + 0x0D,0x4C,0x44,0x54,0x31,0x11,0x00,0x05, /* 000000D8 ".LDT1..." */ + 0x4C,0x31,0x49,0x43,0x01,0x5B,0x82,0x89, /* 000000E0 "L1IC.[.." */ + 0x17,0x01,0x50,0x43,0x49,0x31,0x08,0x5F, /* 000000E8 "..PCI1._" */ + 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0A,0x03, /* 000000F0 "HID.A..." */ + 0x08,0x5F,0x41,0x44,0x52,0x0C,0x00,0x00, /* 000000F8 "._ADR..." */ + 0x18,0x00,0x08,0x5F,0x55,0x49,0x44,0x0A, /* 00000100 "..._UID." */ + 0x02,0x14,0x17,0x5F,0x42,0x42,0x4E,0x00, /* 00000108 "..._BBN." */ + 0xA4,0x47,0x42,0x55,0x53,0x00,0x5E,0x5E, /* 00000110 ".GBUS.^^" */ + 0x2E,0x50,0x43,0x49,0x30,0x53,0x42,0x4C, /* 00000118 ".PCI0SBL" */ + 0x4B,0x14,0x41,0x10,0x5F,0x43,0x52,0x53, /* 00000120 "K.A._CRS" */ + 0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x44, /* 00000128 "..BUF0.D" */ + 0x07,0x0A,0x70,0x47,0x01,0xF8,0x0C,0xF8, /* 00000130 "..pG...." */ + 0x0C,0x01,0x08,0x47,0x01,0x00,0xC0,0x00, /* 00000138 "...G...." */ + 0xC0,0x01,0x80,0x47,0x01,0x80,0xC0,0x80, /* 00000140 "...G...." */ + 0xC0,0x01,0x80,0x88,0x0D,0x00,0x01,0x0C, /* 00000148 "........" */ + 0x03,0x00,0x00,0x00,0x81,0xFF,0xFF,0x00, /* 00000150 "........" */ + 0x00,0x00,0x7F,0x87,0x17,0x00,0x00,0x0C, /* 00000158 "........" */ + 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x0C, /* 00000160 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000168 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x86,0x09,0x00, /* 00000170 "........" */ + 0x01,0x00,0x80,0x0D,0x00,0x00,0x40,0x00, /* 00000178 "......@." */ + 0x00,0x88,0x0D,0x00,0x01,0x0C,0x03,0x00, /* 00000180 "........" */ + 0x00,0x00,0x00,0xAF,0x03,0x00,0x00,0xB0, /* 00000188 "........" */ + 0x03,0x88,0x0D,0x00,0x01,0x0C,0x03,0x00, /* 00000190 "........" */ + 0x00,0xE0,0x03,0xF7,0x0C,0x00,0x00,0x18, /* 00000198 "........" */ + 0x09,0x79,0x00,0x4F,0x53,0x54,0x50,0x8A, /* 000001A0 ".y.OSTP." */ + 0x42,0x55,0x46,0x30,0x0A,0x3E,0x56,0x4C, /* 000001A8 "BUF0.>VL" */ + 0x45,0x4E,0x8A,0x42,0x55,0x46,0x30,0x0A, /* 000001B0 "EN.BUF0." */ + 0x36,0x56,0x4D,0x41,0x58,0x8A,0x42,0x55, /* 000001B8 "6VMAX.BU" */ + 0x46,0x30,0x0A,0x32,0x56,0x4D,0x49,0x4E, /* 000001C0 "F0.2VMIN" */ + 0x79,0x56,0x47,0x41,0x31,0x0A,0x09,0x60, /* 000001C8 "yVGA1..`" */ + 0x72,0x56,0x4D,0x49,0x4E,0x60,0x56,0x4D, /* 000001D0 "rVMIN`VM" */ + 0x41,0x58,0x76,0x56,0x4D,0x41,0x58,0x70, /* 000001D8 "AXvVMAXp" */ + 0x60,0x56,0x4C,0x45,0x4E,0x73,0x47,0x4D, /* 000001E0 "`VLENsGM" */ + 0x45,0x4D,0x00,0x5E,0x5E,0x2E,0x50,0x43, /* 000001E8 "EM.^^.PC" */ + 0x49,0x30,0x53,0x42,0x4C,0x4B,0x42,0x55, /* 000001F0 "I0SBLKBU" */ + 0x46,0x30,0x61,0x73,0x47,0x49,0x4F,0x52, /* 000001F8 "F0asGIOR" */ + 0x00,0x5E,0x5E,0x2E,0x50,0x43,0x49,0x30, /* 00000200 ".^^.PCI0" */ + 0x53,0x42,0x4C,0x4B,0x61,0x62,0x73,0x47, /* 00000208 "SBLKabsG" */ + 0x57,0x42,0x4E,0x00,0x5E,0x5E,0x2E,0x50, /* 00000210 "WBN.^^.P" */ + 0x43,0x49,0x30,0x53,0x42,0x4C,0x4B,0x62, /* 00000218 "CI0SBLKb" */ + 0x63,0xA4,0x63,0x08,0x41,0x50,0x49,0x43, /* 00000220 "c.c.APIC" */ + 0x12,0x34,0x04,0x12,0x0B,0x04,0x0C,0xFF, /* 00000228 ".4......" */ + 0xFF,0x04,0x00,0x00,0x00,0x0A,0x10,0x12, /* 00000230 "........" */ + 0x0B,0x04,0x0C,0xFF,0xFF,0x04,0x00,0x01, /* 00000238 "........" */ + 0x00,0x0A,0x11,0x12,0x0C,0x04,0x0C,0xFF, /* 00000240 "........" */ + 0xFF,0x04,0x00,0x0A,0x02,0x00,0x0A,0x12, /* 00000248 "........" */ + 0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x04,0x00, /* 00000250 "........" */ + 0x0A,0x03,0x00,0x0A,0x13,0x08,0x50,0x49, /* 00000258 "......PI" */ + 0x43,0x4D,0x12,0x3C,0x04,0x12,0x0D,0x04, /* 00000260 "CM.<...." */ + 0x0C,0xFF,0xFF,0x04,0x00,0x00,0x4C,0x4E, /* 00000268 "......LN" */ + 0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF, /* 00000270 "KA......" */ + 0xFF,0x04,0x00,0x01,0x4C,0x4E,0x4B,0x42, /* 00000278 "....LNKB" */ + 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x04, /* 00000280 "........" */ + 0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00, /* 00000288 "...LNKC." */ + 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x04,0x00, /* 00000290 "........" */ + 0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,0x08, /* 00000298 "..LNKD.." */ + 0x44,0x4E,0x43,0x47,0xFF,0x14,0x4B,0x0A, /* 000002A0 "DNCG..K." */ + 0x5F,0x50,0x52,0x54,0x00,0xA0,0x40,0x09, /* 000002A8 "_PRT..@." */ + 0x93,0x44,0x4E,0x43,0x47,0xFF,0x70,0x44, /* 000002B0 ".DNCG.pD" */ + 0x41,0x44,0x44,0x5E,0x5E,0x2E,0x50,0x43, /* 000002B8 "ADD^^.PC" */ + 0x49,0x30,0x53,0x42,0x44,0x4E,0x0C,0xFF, /* 000002C0 "I0SBDN.." */ + 0xFF,0x01,0x00,0x60,0x70,0x60,0x88,0x83, /* 000002C8 "...`p`.." */ + 0x88,0x50,0x49,0x43,0x4D,0x00,0x00,0x00, /* 000002D0 ".PICM..." */ + 0x00,0x70,0x60,0x88,0x83,0x88,0x50,0x49, /* 000002D8 ".p`...PI" */ + 0x43,0x4D,0x01,0x00,0x00,0x00,0x70,0x60, /* 000002E0 "CM....p`" */ + 0x88,0x83,0x88,0x50,0x49,0x43,0x4D,0x0A, /* 000002E8 "...PICM." */ + 0x02,0x00,0x00,0x00,0x70,0x60,0x88,0x83, /* 000002F0 "....p`.." */ + 0x88,0x50,0x49,0x43,0x4D,0x0A,0x03,0x00, /* 000002F8 ".PICM..." */ + 0x00,0x00,0x70,0x60,0x88,0x83,0x88,0x41, /* 00000300 "..p`...A" */ + 0x50,0x49,0x43,0x00,0x00,0x00,0x00,0x70, /* 00000308 "PIC....p" */ + 0x60,0x88,0x83,0x88,0x41,0x50,0x49,0x43, /* 00000310 "`...APIC" */ + 0x01,0x00,0x00,0x00,0x70,0x60,0x88,0x83, /* 00000318 "....p`.." */ + 0x88,0x41,0x50,0x49,0x43,0x0A,0x02,0x00, /* 00000320 ".APIC..." */ + 0x00,0x00,0x70,0x60,0x88,0x83,0x88,0x41, /* 00000328 "..p`...A" */ + 0x50,0x49,0x43,0x0A,0x03,0x00,0x00,0x00, /* 00000330 "PIC....." */ + 0x70,0x00,0x44,0x4E,0x43,0x47,0xA0,0x0B, /* 00000338 "p.DNCG.." */ + 0x92,0x50,0x49,0x43,0x46,0xA4,0x50,0x49, /* 00000340 ".PICF.PI" */ + 0x43,0x4D,0xA1,0x06,0xA4,0x41,0x50,0x49, /* 00000348 "CM...API" */ + 0x43,0x5B,0x82,0x3F,0x53,0x42,0x43,0x33, /* 00000350 "C[.?SBC3" */ + 0x14,0x1C,0x5F,0x41,0x44,0x52,0x00,0xA4, /* 00000358 ".._ADR.." */ + 0x44,0x41,0x44,0x44,0x5E,0x5E,0x5E,0x2E, /* 00000360 "DADD^^^." */ + 0x50,0x43,0x49,0x30,0x53,0x42,0x44,0x4E, /* 00000368 "PCI0SBDN" */ + 0x0C,0x03,0x00,0x01,0x00,0x5B,0x80,0x50, /* 00000370 ".....[.P" */ + 0x49,0x52,0x51,0x02,0x0A,0x56,0x0A,0x02, /* 00000378 "IRQ..V.." */ + 0x5B,0x81,0x10,0x50,0x49,0x52,0x51,0x11, /* 00000380 "[..PIRQ." */ + 0x50,0x49,0x42,0x41,0x08,0x50,0x49,0x44, /* 00000388 "PIBA.PID" */ + 0x43,0x08,0x5B,0x82,0x49,0x04,0x48,0x50, /* 00000390 "C.[.I.HP" */ + 0x45,0x54,0x08,0x48,0x50,0x54,0x5F,0x00, /* 00000398 "ET.HPT_." */ + 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 000003A0 "._HID.A." */ + 0x01,0x03,0x08,0x5F,0x55,0x49,0x44,0x00, /* 000003A8 "..._UID." */ + 0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4, /* 000003B0 ".._STA.." */ + 0x0A,0x0F,0x14,0x22,0x5F,0x43,0x52,0x53, /* 000003B8 "..."_CRS" */ + 0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x11, /* 000003C0 "..BUF0.." */ + 0x0A,0x0E,0x86,0x09,0x00,0x01,0x00,0x00, /* 000003C8 "........" */ + 0xD0,0xFE,0x00,0x04,0x00,0x00,0x79,0x00, /* 000003D0 "......y." */ + 0xA4,0x42,0x55,0x46,0x30,0x5B,0x82,0x47, /* 000003D8 ".BUF0[.G" */ + 0x17,0x4C,0x4E,0x4B,0x41,0x08,0x5F,0x48, /* 000003E0 ".LNKA._H" */ + 0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08, /* 000003E8 "ID.A...." */ + 0x5F,0x55,0x49,0x44,0x01,0x14,0x22,0x5F, /* 000003F0 "_UID.."_" */ + 0x53,0x54,0x41,0x00,0x7B,0x5E,0x5E,0x2E, /* 000003F8 "STA.{^^." */ + 0x53,0x42,0x43,0x33,0x50,0x49,0x42,0x41, /* 00000400 "SBC3PIBA" */ + 0x0A,0x0F,0x60,0xA0,0x07,0x93,0x60,0x00, /* 00000408 "..`...`." */ + 0xA4,0x0A,0x09,0xA1,0x04,0xA4,0x0A,0x0B, /* 00000410 "........" */ + 0x14,0x1A,0x5F,0x50,0x52,0x53,0x00,0x08, /* 00000418 ".._PRS.." */ + 0x42,0x55,0x46,0x41,0x11,0x09,0x0A,0x06, /* 00000420 "BUFA...." */ + 0x23,0x28,0x0C,0x18,0x79,0x00,0xA4,0x42, /* 00000428 "#(..y..B" */ + 0x55,0x46,0x41,0x14,0x47,0x04,0x5F,0x44, /* 00000430 "UFA.G._D" */ + 0x49,0x53,0x00,0x70,0x01,0x63,0x7B,0x5E, /* 00000438 "IS.p.c{^" */ + 0x5E,0x2E,0x53,0x42,0x43,0x33,0x50,0x49, /* 00000440 "^.SBC3PI" */ + 0x42,0x41,0x0A,0x0F,0x61,0x70,0x61,0x62, /* 00000448 "BA..apab" */ + 0xA0,0x0A,0x94,0x61,0x0A,0x07,0x74,0x61, /* 00000450 "...a..ta" */ + 0x0A,0x08,0x61,0x79,0x63,0x61,0x63,0x80, /* 00000458 "..aycac." */ + 0x63,0x63,0x7B,0x5E,0x5E,0x2E,0x53,0x42, /* 00000460 "cc{^^.SB" */ + 0x43,0x33,0x50,0x49,0x42,0x41,0x0A,0xF0, /* 00000468 "C3PIBA.." */ + 0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33,0x50, /* 00000470 "^^.SBC3P" */ + 0x49,0x42,0x41,0x14,0x41,0x07,0x5F,0x43, /* 00000478 "IBA.A._C" */ + 0x52,0x53,0x00,0x08,0x42,0x55,0x46,0x41, /* 00000480 "RS..BUFA" */ + 0x11,0x09,0x0A,0x06,0x23,0x00,0x00,0x18, /* 00000488 "....#..." */ + 0x79,0x00,0x8C,0x42,0x55,0x46,0x41,0x01, /* 00000490 "y..BUFA." */ + 0x49,0x52,0x41,0x31,0x8C,0x42,0x55,0x46, /* 00000498 "IRA1.BUF" */ + 0x41,0x0A,0x02,0x49,0x52,0x41,0x32,0x70, /* 000004A0 "A..IRA2p" */ + 0x00,0x63,0x70,0x00,0x64,0x7B,0x5E,0x5E, /* 000004A8 ".cp.d{^^" */ + 0x2E,0x53,0x42,0x43,0x33,0x50,0x49,0x42, /* 000004B0 ".SBC3PIB" */ + 0x41,0x0A,0x0F,0x61,0xA0,0x2B,0x92,0x93, /* 000004B8 "A..a.+.." */ + 0x61,0x00,0xA0,0x0E,0x94,0x61,0x0A,0x07, /* 000004C0 "a....a.." */ + 0x74,0x61,0x0A,0x08,0x62,0x79,0x01,0x62, /* 000004C8 "ta..by.b" */ + 0x64,0xA1,0x0A,0xA0,0x08,0x94,0x61,0x00, /* 000004D0 "d.....a." */ + 0x79,0x01,0x61,0x63,0x70,0x63,0x49,0x52, /* 000004D8 "y.acpcIR" */ + 0x41,0x31,0x70,0x64,0x49,0x52,0x41,0x32, /* 000004E0 "A1pdIRA2" */ + 0xA4,0x42,0x55,0x46,0x41,0x14,0x48,0x06, /* 000004E8 ".BUFA.H." */ + 0x5F,0x53,0x52,0x53,0x01,0x8C,0x68,0x01, /* 000004F0 "_SRS..h." */ + 0x49,0x52,0x41,0x31,0x8C,0x68,0x0A,0x02, /* 000004F8 "IRA1.h.." */ + 0x49,0x52,0x41,0x32,0x79,0x49,0x52,0x41, /* 00000500 "IRA2yIRA" */ + 0x32,0x0A,0x08,0x60,0x7D,0x60,0x49,0x52, /* 00000508 "2..`}`IR" */ + 0x41,0x31,0x60,0x70,0x00,0x61,0x7A,0x60, /* 00000510 "A1`p.az`" */ + 0x01,0x60,0xA2,0x0A,0x94,0x60,0x00,0x75, /* 00000518 ".`...`.u" */ + 0x61,0x7A,0x60,0x01,0x60,0x7B,0x5E,0x5E, /* 00000520 "az`.`{^^" */ + 0x2E,0x53,0x42,0x43,0x33,0x50,0x49,0x42, /* 00000528 ".SBC3PIB" */ + 0x41,0x0A,0xF0,0x5E,0x5E,0x2E,0x53,0x42, /* 00000530 "A..^^.SB" */ + 0x43,0x33,0x50,0x49,0x42,0x41,0x7D,0x5E, /* 00000538 "C3PIBA}^" */ + 0x5E,0x2E,0x53,0x42,0x43,0x33,0x50,0x49, /* 00000540 "^.SBC3PI" */ + 0x42,0x41,0x61,0x5E,0x5E,0x2E,0x53,0x42, /* 00000548 "BAa^^.SB" */ + 0x43,0x33,0x50,0x49,0x42,0x41,0x5B,0x82, /* 00000550 "C3PIBA[." */ + 0x47,0x18,0x4C,0x4E,0x4B,0x42,0x08,0x5F, /* 00000558 "G.LNKB._" */ + 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F, /* 00000560 "HID.A..." */ + 0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x14, /* 00000568 "._UID..." */ + 0x22,0x5F,0x53,0x54,0x41,0x00,0x7B,0x5E, /* 00000570 ""_STA.{^" */ + 0x5E,0x2E,0x53,0x42,0x43,0x33,0x50,0x49, /* 00000578 "^.SBC3PI" */ + 0x42,0x41,0x0A,0xF0,0x60,0xA0,0x07,0x93, /* 00000580 "BA..`..." */ + 0x60,0x00,0xA4,0x0A,0x09,0xA1,0x04,0xA4, /* 00000588 "`......." */ + 0x0A,0x0B,0x14,0x1A,0x5F,0x50,0x52,0x53, /* 00000590 "...._PRS" */ + 0x00,0x08,0x42,0x55,0x46,0x42,0x11,0x09, /* 00000598 "..BUFB.." */ + 0x0A,0x06,0x23,0x28,0x0C,0x18,0x79,0x00, /* 000005A0 "..#(..y." */ + 0xA4,0x42,0x55,0x46,0x42,0x14,0x4C,0x04, /* 000005A8 ".BUFB.L." */ + 0x5F,0x44,0x49,0x53,0x00,0x70,0x01,0x63, /* 000005B0 "_DIS.p.c" */ + 0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33, /* 000005B8 "{^^.SBC3" */ + 0x50,0x49,0x42,0x41,0x0A,0xF0,0x61,0x7A, /* 000005C0 "PIBA..az" */ + 0x61,0x0A,0x04,0x61,0x70,0x61,0x62,0xA0, /* 000005C8 "a..apab." */ + 0x0A,0x94,0x61,0x0A,0x07,0x74,0x61,0x0A, /* 000005D0 "..a..ta." */ + 0x08,0x61,0x79,0x63,0x61,0x63,0x80,0x63, /* 000005D8 ".aycac.c" */ + 0x63,0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 000005E0 "c{^^.SBC" */ + 0x33,0x50,0x49,0x42,0x41,0x0A,0x0F,0x5E, /* 000005E8 "3PIBA..^" */ + 0x5E,0x2E,0x53,0x42,0x43,0x33,0x50,0x49, /* 000005F0 "^.SBC3PI" */ + 0x42,0x41,0x14,0x46,0x07,0x5F,0x43,0x52, /* 000005F8 "BA.F._CR" */ + 0x53,0x00,0x08,0x42,0x55,0x46,0x42,0x11, /* 00000600 "S..BUFB." */ + 0x09,0x0A,0x06,0x23,0x00,0x00,0x18,0x79, /* 00000608 "...#...y" */ + 0x00,0x8C,0x42,0x55,0x46,0x42,0x01,0x49, /* 00000610 "..BUFB.I" */ + 0x52,0x42,0x31,0x8C,0x42,0x55,0x46,0x42, /* 00000618 "RB1.BUFB" */ + 0x0A,0x02,0x49,0x52,0x42,0x32,0x70,0x00, /* 00000620 "..IRB2p." */ + 0x63,0x70,0x00,0x64,0x7B,0x5E,0x5E,0x2E, /* 00000628 "cp.d{^^." */ + 0x53,0x42,0x43,0x33,0x50,0x49,0x42,0x41, /* 00000630 "SBC3PIBA" */ + 0x0A,0xF0,0x61,0x7A,0x61,0x0A,0x04,0x61, /* 00000638 "..aza..a" */ + 0xA0,0x2B,0x92,0x93,0x61,0x00,0xA0,0x0E, /* 00000640 ".+..a..." */ + 0x94,0x61,0x0A,0x07,0x74,0x61,0x0A,0x08, /* 00000648 ".a..ta.." */ + 0x62,0x79,0x01,0x62,0x64,0xA1,0x0A,0xA0, /* 00000650 "by.bd..." */ + 0x08,0x94,0x61,0x00,0x79,0x01,0x61,0x63, /* 00000658 "..a.y.ac" */ + 0x70,0x63,0x49,0x52,0x42,0x31,0x70,0x64, /* 00000660 "pcIRB1pd" */ + 0x49,0x52,0x42,0x32,0xA4,0x42,0x55,0x46, /* 00000668 "IRB2.BUF" */ + 0x42,0x14,0x4D,0x06,0x5F,0x53,0x52,0x53, /* 00000670 "B.M._SRS" */ + 0x01,0x8C,0x68,0x01,0x49,0x52,0x42,0x31, /* 00000678 "..h.IRB1" */ + 0x8C,0x68,0x0A,0x02,0x49,0x52,0x42,0x32, /* 00000680 ".h..IRB2" */ + 0x79,0x49,0x52,0x42,0x32,0x0A,0x08,0x60, /* 00000688 "yIRB2..`" */ + 0x7D,0x60,0x49,0x52,0x42,0x31,0x60,0x70, /* 00000690 "}`IRB1`p" */ + 0x00,0x61,0x7A,0x60,0x01,0x60,0xA2,0x0A, /* 00000698 ".az`.`.." */ + 0x94,0x60,0x00,0x75,0x61,0x7A,0x60,0x01, /* 000006A0 ".`.uaz`." */ + 0x60,0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 000006A8 "`{^^.SBC" */ + 0x33,0x50,0x49,0x42,0x41,0x0A,0x0F,0x5E, /* 000006B0 "3PIBA..^" */ + 0x5E,0x2E,0x53,0x42,0x43,0x33,0x50,0x49, /* 000006B8 "^.SBC3PI" */ + 0x42,0x41,0x79,0x61,0x0A,0x04,0x61,0x7D, /* 000006C0 "BAya..a}" */ + 0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33,0x50, /* 000006C8 "^^.SBC3P" */ + 0x49,0x42,0x41,0x61,0x5E,0x5E,0x2E,0x53, /* 000006D0 "IBAa^^.S" */ + 0x42,0x43,0x33,0x50,0x49,0x42,0x41,0x5B, /* 000006D8 "BC3PIBA[" */ + 0x82,0x48,0x17,0x4C,0x4E,0x4B,0x43,0x08, /* 000006E0 ".H.LNKC." */ + 0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C, /* 000006E8 "_HID.A.." */ + 0x0F,0x08,0x5F,0x55,0x49,0x44,0x0A,0x03, /* 000006F0 ".._UID.." */ + 0x14,0x22,0x5F,0x53,0x54,0x41,0x00,0x7B, /* 000006F8 "."_STA.{" */ + 0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33,0x50, /* 00000700 "^^.SBC3P" */ + 0x49,0x44,0x43,0x0A,0x0F,0x60,0xA0,0x07, /* 00000708 "IDC..`.." */ + 0x93,0x60,0x00,0xA4,0x0A,0x09,0xA1,0x04, /* 00000710 ".`......" */ + 0xA4,0x0A,0x0B,0x14,0x1A,0x5F,0x50,0x52, /* 00000718 "....._PR" */ + 0x53,0x00,0x08,0x42,0x55,0x46,0x41,0x11, /* 00000720 "S..BUFA." */ + 0x09,0x0A,0x06,0x23,0x28,0x0C,0x18,0x79, /* 00000728 "...#(..y" */ + 0x00,0xA4,0x42,0x55,0x46,0x41,0x14,0x47, /* 00000730 "..BUFA.G" */ + 0x04,0x5F,0x44,0x49,0x53,0x00,0x70,0x01, /* 00000738 "._DIS.p." */ + 0x63,0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 00000740 "c{^^.SBC" */ + 0x33,0x50,0x49,0x44,0x43,0x0A,0x0F,0x61, /* 00000748 "3PIDC..a" */ + 0x70,0x61,0x62,0xA0,0x0A,0x94,0x61,0x0A, /* 00000750 "pab...a." */ + 0x07,0x74,0x61,0x0A,0x08,0x61,0x79,0x63, /* 00000758 ".ta..ayc" */ + 0x61,0x63,0x80,0x63,0x63,0x7B,0x5E,0x5E, /* 00000760 "ac.cc{^^" */ + 0x2E,0x53,0x42,0x43,0x33,0x50,0x49,0x44, /* 00000768 ".SBC3PID" */ + 0x43,0x0A,0xF0,0x5E,0x5E,0x2E,0x53,0x42, /* 00000770 "C..^^.SB" */ + 0x43,0x33,0x50,0x49,0x44,0x43,0x14,0x41, /* 00000778 "C3PIDC.A" */ + 0x07,0x5F,0x43,0x52,0x53,0x00,0x08,0x42, /* 00000780 "._CRS..B" */ + 0x55,0x46,0x41,0x11,0x09,0x0A,0x06,0x23, /* 00000788 "UFA....#" */ + 0x00,0x00,0x18,0x79,0x00,0x8C,0x42,0x55, /* 00000790 "...y..BU" */ + 0x46,0x41,0x01,0x49,0x52,0x41,0x31,0x8C, /* 00000798 "FA.IRA1." */ + 0x42,0x55,0x46,0x41,0x0A,0x02,0x49,0x52, /* 000007A0 "BUFA..IR" */ + 0x41,0x32,0x70,0x00,0x63,0x70,0x00,0x64, /* 000007A8 "A2p.cp.d" */ + 0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33, /* 000007B0 "{^^.SBC3" */ + 0x50,0x49,0x44,0x43,0x0A,0x0F,0x61,0xA0, /* 000007B8 "PIDC..a." */ + 0x2B,0x92,0x93,0x61,0x00,0xA0,0x0E,0x94, /* 000007C0 "+..a...." */ + 0x61,0x0A,0x07,0x74,0x61,0x0A,0x08,0x62, /* 000007C8 "a..ta..b" */ + 0x79,0x01,0x62,0x64,0xA1,0x0A,0xA0,0x08, /* 000007D0 "y.bd...." */ + 0x94,0x61,0x00,0x79,0x01,0x61,0x63,0x70, /* 000007D8 ".a.y.acp" */ + 0x63,0x49,0x52,0x41,0x31,0x70,0x64,0x49, /* 000007E0 "cIRA1pdI" */ + 0x52,0x41,0x32,0xA4,0x42,0x55,0x46,0x41, /* 000007E8 "RA2.BUFA" */ + 0x14,0x48,0x06,0x5F,0x53,0x52,0x53,0x01, /* 000007F0 ".H._SRS." */ + 0x8C,0x68,0x01,0x49,0x52,0x41,0x31,0x8C, /* 000007F8 ".h.IRA1." */ + 0x68,0x0A,0x02,0x49,0x52,0x41,0x32,0x79, /* 00000800 "h..IRA2y" */ + 0x49,0x52,0x41,0x32,0x0A,0x08,0x60,0x7D, /* 00000808 "IRA2..`}" */ + 0x60,0x49,0x52,0x41,0x31,0x60,0x70,0x00, /* 00000810 "`IRA1`p." */ + 0x61,0x7A,0x60,0x01,0x60,0xA2,0x0A,0x94, /* 00000818 "az`.`..." */ + 0x60,0x00,0x75,0x61,0x7A,0x60,0x01,0x60, /* 00000820 "`.uaz`.`" */ + 0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33, /* 00000828 "{^^.SBC3" */ + 0x50,0x49,0x44,0x43,0x0A,0xF0,0x5E,0x5E, /* 00000830 "PIDC..^^" */ + 0x2E,0x53,0x42,0x43,0x33,0x50,0x49,0x44, /* 00000838 ".SBC3PID" */ + 0x43,0x7D,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 00000840 "C}^^.SBC" */ + 0x33,0x50,0x49,0x44,0x43,0x61,0x5E,0x5E, /* 00000848 "3PIDCa^^" */ + 0x2E,0x53,0x42,0x43,0x33,0x50,0x49,0x44, /* 00000850 ".SBC3PID" */ + 0x43,0x5B,0x82,0x47,0x18,0x4C,0x4E,0x4B, /* 00000858 "C[.G.LNK" */ + 0x44,0x08,0x5F,0x48,0x49,0x44,0x0C,0x41, /* 00000860 "D._HID.A" */ + 0xD0,0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44, /* 00000868 "...._UID" */ + 0x0A,0x04,0x14,0x22,0x5F,0x53,0x54,0x41, /* 00000870 "..."_STA" */ + 0x00,0x7B,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 00000878 ".{^^.SBC" */ + 0x33,0x50,0x49,0x44,0x43,0x0A,0xF0,0x60, /* 00000880 "3PIDC..`" */ + 0xA0,0x07,0x93,0x60,0x00,0xA4,0x0A,0x09, /* 00000888 "...`...." */ + 0xA1,0x04,0xA4,0x0A,0x0B,0x14,0x1A,0x5F, /* 00000890 "......._" */ + 0x50,0x52,0x53,0x00,0x08,0x42,0x55,0x46, /* 00000898 "PRS..BUF" */ + 0x42,0x11,0x09,0x0A,0x06,0x23,0x28,0x0C, /* 000008A0 "B....#(." */ + 0x18,0x79,0x00,0xA4,0x42,0x55,0x46,0x42, /* 000008A8 ".y..BUFB" */ + 0x14,0x4C,0x04,0x5F,0x44,0x49,0x53,0x00, /* 000008B0 ".L._DIS." */ + 0x70,0x01,0x63,0x7B,0x5E,0x5E,0x2E,0x53, /* 000008B8 "p.c{^^.S" */ + 0x42,0x43,0x33,0x50,0x49,0x44,0x43,0x0A, /* 000008C0 "BC3PIDC." */ + 0xF0,0x61,0x7A,0x61,0x0A,0x04,0x61,0x70, /* 000008C8 ".aza..ap" */ + 0x61,0x62,0xA0,0x0A,0x94,0x61,0x0A,0x07, /* 000008D0 "ab...a.." */ + 0x74,0x61,0x0A,0x08,0x61,0x79,0x63,0x61, /* 000008D8 "ta..ayca" */ + 0x63,0x80,0x63,0x63,0x7B,0x5E,0x5E,0x2E, /* 000008E0 "c.cc{^^." */ + 0x53,0x42,0x43,0x33,0x50,0x49,0x44,0x43, /* 000008E8 "SBC3PIDC" */ + 0x0A,0x0F,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 000008F0 "..^^.SBC" */ + 0x33,0x50,0x49,0x44,0x43,0x14,0x46,0x07, /* 000008F8 "3PIDC.F." */ + 0x5F,0x43,0x52,0x53,0x00,0x08,0x42,0x55, /* 00000900 "_CRS..BU" */ + 0x46,0x42,0x11,0x09,0x0A,0x06,0x23,0x00, /* 00000908 "FB....#." */ + 0x00,0x18,0x79,0x00,0x8C,0x42,0x55,0x46, /* 00000910 "..y..BUF" */ + 0x42,0x01,0x49,0x52,0x42,0x31,0x8C,0x42, /* 00000918 "B.IRB1.B" */ + 0x55,0x46,0x42,0x0A,0x02,0x49,0x52,0x42, /* 00000920 "UFB..IRB" */ + 0x32,0x70,0x00,0x63,0x70,0x00,0x64,0x7B, /* 00000928 "2p.cp.d{" */ + 0x5E,0x5E,0x2E,0x53,0x42,0x43,0x33,0x50, /* 00000930 "^^.SBC3P" */ + 0x49,0x44,0x43,0x0A,0xF0,0x61,0x7A,0x61, /* 00000938 "IDC..aza" */ + 0x0A,0x04,0x61,0xA0,0x2B,0x92,0x93,0x61, /* 00000940 "..a.+..a" */ + 0x00,0xA0,0x0E,0x94,0x61,0x0A,0x07,0x74, /* 00000948 "....a..t" */ + 0x61,0x0A,0x08,0x62,0x79,0x01,0x62,0x64, /* 00000950 "a..by.bd" */ + 0xA1,0x0A,0xA0,0x08,0x94,0x61,0x00,0x79, /* 00000958 ".....a.y" */ + 0x01,0x61,0x63,0x70,0x63,0x49,0x52,0x42, /* 00000960 ".acpcIRB" */ + 0x31,0x70,0x64,0x49,0x52,0x42,0x32,0xA4, /* 00000968 "1pdIRB2." */ + 0x42,0x55,0x46,0x42,0x14,0x4D,0x06,0x5F, /* 00000970 "BUFB.M._" */ + 0x53,0x52,0x53,0x01,0x8C,0x68,0x01,0x49, /* 00000978 "SRS..h.I" */ + 0x52,0x42,0x31,0x8C,0x68,0x0A,0x02,0x49, /* 00000980 "RB1.h..I" */ + 0x52,0x42,0x32,0x79,0x49,0x52,0x42,0x32, /* 00000988 "RB2yIRB2" */ + 0x0A,0x08,0x60,0x7D,0x60,0x49,0x52,0x42, /* 00000990 "..`}`IRB" */ + 0x31,0x60,0x70,0x00,0x61,0x7A,0x60,0x01, /* 00000998 "1`p.az`." */ + 0x60,0xA2,0x0A,0x94,0x60,0x00,0x75,0x61, /* 000009A0 "`...`.ua" */ + 0x7A,0x60,0x01,0x60,0x7B,0x5E,0x5E,0x2E, /* 000009A8 "z`.`{^^." */ + 0x53,0x42,0x43,0x33,0x50,0x49,0x44,0x43, /* 000009B0 "SBC3PIDC" */ + 0x0A,0x0F,0x5E,0x5E,0x2E,0x53,0x42,0x43, /* 000009B8 "..^^.SBC" */ + 0x33,0x50,0x49,0x44,0x43,0x79,0x61,0x0A, /* 000009C0 "3PIDCya." */ + 0x04,0x61,0x7D,0x5E,0x5E,0x2E,0x53,0x42, /* 000009C8 ".a}^^.SB" */ + 0x43,0x33,0x50,0x49,0x44,0x43,0x61,0x5E, /* 000009D0 "C3PIDCa^" */ + 0x5E,0x2E,0x53,0x42,0x43,0x33,0x50,0x49, /* 000009D8 "^.SBC3PI" */ + 0x44,0x43,0x5B,0x82,0x4A,0x33,0x49,0x53, /* 000009E0 "DC[.J3IS" */ + 0x41,0x5F,0x14,0x1C,0x5F,0x41,0x44,0x52, /* 000009E8 "A_.._ADR" */ + 0x00,0xA4,0x44,0x41,0x44,0x44,0x5E,0x5E, /* 000009F0 "..DADD^^" */ + 0x5E,0x2E,0x50,0x43,0x49,0x30,0x53,0x42, /* 000009F8 "^.PCI0SB" */ + 0x44,0x4E,0x0C,0x00,0x00,0x01,0x00,0x5B, /* 00000A00 "DN.....[" */ + 0x80,0x50,0x49,0x52,0x59,0x02,0x0A,0x51, /* 00000A08 ".PIRY..Q" */ + 0x0A,0x02,0x5B,0x81,0x32,0x50,0x49,0x52, /* 00000A10 "..[.2PIR" */ + 0x59,0x01,0x5A,0x30,0x30,0x30,0x02,0x00, /* 00000A18 "Y.Z000.." */ + 0x01,0x45,0x43,0x50,0x5F,0x01,0x46,0x44, /* 00000A20 ".ECP_.FD" */ + 0x43,0x31,0x01,0x46,0x44,0x43,0x32,0x01, /* 00000A28 "C1.FDC2." */ + 0x00,0x02,0x5A,0x30,0x30,0x31,0x03,0x53, /* 00000A30 "..Z001.S" */ + 0x41,0x45,0x4E,0x01,0x5A,0x30,0x30,0x32, /* 00000A38 "AEN.Z002" */ + 0x03,0x53,0x42,0x45,0x4E,0x01,0x5B,0x82, /* 00000A40 ".SBEN.[." */ + 0x2C,0x50,0x49,0x43,0x5F,0x08,0x5F,0x48, /* 00000A48 ",PIC_._H" */ + 0x49,0x44,0x0B,0x41,0xD0,0x08,0x5F,0x43, /* 00000A50 "ID.A.._C" */ + 0x52,0x53,0x11,0x19,0x0A,0x16,0x47,0x01, /* 00000A58 "RS....G." */ + 0x20,0x00,0x20,0x00,0x01,0x02,0x47,0x01, /* 00000A60 " . ...G." */ + 0xA0,0x00,0xA0,0x00,0x01,0x02,0x23,0x04, /* 00000A68 "......#." */ + 0x00,0x01,0x79,0x00,0x5B,0x82,0x35,0x44, /* 00000A70 "..y.[.5D" */ + 0x4D,0x41,0x31,0x08,0x5F,0x48,0x49,0x44, /* 00000A78 "MA1._HID" */ + 0x0C,0x41,0xD0,0x02,0x00,0x08,0x5F,0x43, /* 00000A80 ".A...._C" */ + 0x52,0x53,0x11,0x20,0x0A,0x1D,0x47,0x01, /* 00000A88 "RS. ..G." */ + 0x00,0x00,0x00,0x00,0x01,0x10,0x47,0x01, /* 00000A90 "......G." */ + 0x80,0x00,0x80,0x00,0x01,0x10,0x47,0x01, /* 00000A98 "......G." */ + 0xC0,0x00,0xC0,0x00,0x01,0x20,0x2A,0x10, /* 00000AA0 "..... *." */ + 0x02,0x79,0x00,0x5B,0x82,0x26,0x54,0x4D, /* 00000AA8 ".y.[.&TM" */ + 0x52,0x5F,0x08,0x5F,0x48,0x49,0x44,0x0C, /* 00000AB0 "R_._HID." */ + 0x41,0xD0,0x01,0x00,0x08,0x5F,0x43,0x52, /* 00000AB8 "A...._CR" */ + 0x53,0x11,0x11,0x0A,0x0E,0x47,0x01,0x40, /* 00000AC0 "S....G.@" */ + 0x00,0x40,0x00,0x01,0x04,0x23,0x01,0x00, /* 00000AC8 ".@...#.." */ + 0x01,0x79,0x00,0x5B,0x82,0x26,0x52,0x54, /* 00000AD0 ".y.[.&RT" */ + 0x43,0x5F,0x08,0x5F,0x48,0x49,0x44,0x0C, /* 00000AD8 "C_._HID." */ + 0x41,0xD0,0x0B,0x00,0x08,0x5F,0x43,0x52, /* 00000AE0 "A...._CR" */ + 0x53,0x11,0x11,0x0A,0x0E,0x47,0x01,0x70, /* 00000AE8 "S....G.p" */ + 0x00,0x70,0x00,0x01,0x06,0x23,0x00,0x01, /* 00000AF0 ".p...#.." */ + 0x01,0x79,0x00,0x5B,0x82,0x22,0x53,0x50, /* 00000AF8 ".y.[."SP" */ + 0x4B,0x52,0x08,0x5F,0x48,0x49,0x44,0x0C, /* 00000B00 "KR._HID." */ + 0x41,0xD0,0x08,0x00,0x08,0x5F,0x43,0x52, /* 00000B08 "A...._CR" */ + 0x53,0x11,0x0D,0x0A,0x0A,0x47,0x01,0x61, /* 00000B10 "S....G.a" */ + 0x00,0x61,0x00,0x01,0x01,0x79,0x00,0x5B, /* 00000B18 ".a...y.[" */ + 0x82,0x26,0x43,0x4F,0x50,0x52,0x08,0x5F, /* 00000B20 ".&COPR._" */ + 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x04, /* 00000B28 "HID.A..." */ + 0x08,0x5F,0x43,0x52,0x53,0x11,0x11,0x0A, /* 00000B30 "._CRS..." */ + 0x0E,0x47,0x01,0xF0,0x00,0xF0,0x00,0x01, /* 00000B38 ".G......" */ + 0x10,0x23,0x00,0x20,0x01,0x79,0x00,0x5B, /* 00000B40 ".#. .y.[" */ + 0x82,0x4E,0x09,0x53,0x59,0x53,0x52,0x08, /* 00000B48 ".N.SYSR." */ + 0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C, /* 00000B50 "_HID.A.." */ + 0x02,0x08,0x5F,0x55,0x49,0x44,0x00,0x08, /* 00000B58 ".._UID.." */ + 0x53,0x59,0x52,0x31,0x11,0x46,0x07,0x0A, /* 00000B60 "SYR1.F.." */ + 0x72,0x47,0x01,0xD0,0x04,0xD0,0x04,0x01, /* 00000B68 "rG......" */ + 0x02,0x47,0x01,0x00,0x11,0x7F,0x11,0x01, /* 00000B70 ".G......" */ + 0x80,0x47,0x01,0x80,0x11,0xFF,0x11,0x01, /* 00000B78 ".G......" */ + 0x80,0x47,0x01,0x10,0x00,0x10,0x00,0x01, /* 00000B80 ".G......" */ + 0x10,0x47,0x01,0x22,0x00,0x22,0x00,0x01, /* 00000B88 ".G.".".." */ + 0x1E,0x47,0x01,0x44,0x00,0x44,0x00,0x01, /* 00000B90 ".G.D.D.." */ + 0x1C,0x47,0x01,0x62,0x00,0x62,0x00,0x01, /* 00000B98 ".G.b.b.." */ + 0x02,0x47,0x01,0x65,0x00,0x65,0x00,0x01, /* 00000BA0 ".G.e.e.." */ + 0x0B,0x47,0x01,0x76,0x00,0x76,0x00,0x01, /* 00000BA8 ".G.v.v.." */ + 0x0A,0x47,0x01,0x90,0x00,0x90,0x00,0x01, /* 00000BB0 ".G......" */ + 0x10,0x47,0x01,0xA2,0x00,0xA2,0x00,0x01, /* 00000BB8 ".G......" */ + 0x1E,0x47,0x01,0xE0,0x00,0xE0,0x00,0x01, /* 00000BC0 ".G......" */ + 0x10,0x47,0x01,0x78,0x0B,0x78,0x0B,0x01, /* 00000BC8 ".G.x.x.." */ + 0x04,0x47,0x01,0x90,0x01,0x90,0x01,0x01, /* 00000BD0 ".G......" */ + 0x04,0x79,0x00,0x14,0x0B,0x5F,0x43,0x52, /* 00000BD8 ".y..._CR" */ + 0x53,0x00,0xA4,0x53,0x59,0x52,0x31,0x5B, /* 00000BE0 "S..SYR1[" */ + 0x82,0x4B,0x0C,0x4D,0x45,0x4D,0x5F,0x08, /* 00000BE8 ".K.MEM_." */ + 0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C, /* 00000BF0 "_HID.A.." */ + 0x02,0x08,0x5F,0x55,0x49,0x44,0x01,0x14, /* 00000BF8 ".._UID.." */ + 0x44,0x0B,0x5F,0x43,0x52,0x53,0x00,0x08, /* 00000C00 "D._CRS.." */ + 0x42,0x55,0x46,0x30,0x11,0x4E,0x07,0x0A, /* 00000C08 "BUF0.N.." */ + 0x7A,0x86,0x09,0x00,0x01,0x00,0x00,0x0E, /* 00000C10 "z......." */ + 0x00,0x00,0x00,0x02,0x00,0x86,0x09,0x00, /* 00000C18 "........" */ + 0x01,0x00,0x00,0x0C,0x00,0x00,0x00,0x00, /* 00000C20 "........" */ + 0x00,0x86,0x09,0x00,0x01,0x00,0x00,0xC0, /* 00000C28 "........" */ + 0xFE,0x00,0x10,0x00,0x00,0x86,0x09,0x00, /* 00000C30 "........" */ + 0x01,0x00,0x00,0xC0,0xFF,0x00,0x00,0x38, /* 00000C38 ".......8" */ + 0x00,0x86,0x09,0x00,0x01,0x00,0x00,0xE0, /* 00000C40 "........" */ + 0xFE,0x00,0x10,0x00,0x00,0x86,0x09,0x00, /* 00000C48 "........" */ + 0x01,0x00,0x00,0xF8,0xFF,0x00,0x00,0x08, /* 00000C50 "........" */ + 0x00,0x86,0x09,0x00,0x01,0x00,0x00,0x00, /* 00000C58 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x86,0x09,0x00, /* 00000C60 "........" */ + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000C68 "........" */ + 0x00,0x86,0x09,0x00,0x01,0x00,0x00,0x00, /* 00000C70 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x86,0x09,0x00, /* 00000C78 "........" */ + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000C80 "........" */ + 0x00,0x79,0x00,0x8A,0x42,0x55,0x46,0x30, /* 00000C88 ".y..BUF0" */ + 0x0A,0x14,0x43,0x4C,0x45,0x4E,0x8A,0x42, /* 00000C90 "..CLEN.B" */ + 0x55,0x46,0x30,0x0A,0x10,0x43,0x42,0x41, /* 00000C98 "UF0..CBA" */ + 0x53,0x79,0x56,0x47,0x41,0x31,0x0A,0x09, /* 00000CA0 "SyVGA1.." */ + 0x60,0x70,0x60,0x43,0x4C,0x45,0x4E,0xA4, /* 00000CA8 "`p`CLEN." */ + 0x42,0x55,0x46,0x30,0x5B,0x82,0x39,0x50, /* 00000CB0 "BUF0[.9P" */ + 0x53,0x32,0x4D,0x08,0x5F,0x48,0x49,0x44, /* 00000CB8 "S2M._HID" */ + 0x0C,0x41,0xD0,0x0F,0x13,0x08,0x5F,0x43, /* 00000CC0 ".A...._C" */ + 0x52,0x53,0x11,0x08,0x0A,0x05,0x22,0x00, /* 00000CC8 "RS...."." */ + 0x10,0x79,0x00,0x14,0x1B,0x5F,0x53,0x54, /* 00000CD0 ".y..._ST" */ + 0x41,0x00,0x7B,0x46,0x4C,0x47,0x30,0x0A, /* 00000CD8 "A.{FLG0." */ + 0x04,0x60,0xA0,0x08,0x93,0x60,0x0A,0x04, /* 00000CE0 ".`...`.." */ + 0xA4,0x0A,0x0F,0xA1,0x03,0xA4,0x00,0x5B, /* 00000CE8 ".......[" */ + 0x82,0x2D,0x50,0x53,0x32,0x4B,0x08,0x5F, /* 00000CF0 ".-PS2K._" */ + 0x48,0x49,0x44,0x0C,0x41,0xD0,0x03,0x03, /* 00000CF8 "HID.A..." */ + 0x08,0x5F,0x43,0x52,0x53,0x11,0x18,0x0A, /* 00000D00 "._CRS..." */ + 0x15,0x47,0x01,0x60,0x00,0x60,0x00,0x01, /* 00000D08 ".G.`.`.." */ + 0x01,0x47,0x01,0x64,0x00,0x64,0x00,0x01, /* 00000D10 ".G.d.d.." */ + 0x01,0x22,0x02,0x00,0x79,0x00,0x5B,0x82, /* 00000D18 "."..y.[." */ + 0x4C,0x1F,0x54,0x50,0x32,0x50,0x14,0x18, /* 00000D20 "L.TP2P.." */ + 0x5F,0x41,0x44,0x52,0x00,0xA4,0x44,0x41, /* 00000D28 "_ADR..DA" */ + 0x44,0x44,0x5E,0x5E,0x5E,0x2E,0x50,0x43, /* 00000D30 "DD^^^.PC" */ + 0x49,0x30,0x53,0x42,0x44,0x4E,0x00,0x14, /* 00000D38 "I0SBDN.." */ + 0x20,0x5F,0x50,0x52,0x57,0x00,0xA0,0x10, /* 00000D40 " _PRW..." */ + 0x5B,0x12,0x5F,0x53,0x33,0x5F,0x60,0xA4, /* 00000D48 "[._S3_`." */ + 0x12,0x06,0x02,0x0A,0x08,0x0A,0x03,0xA1, /* 00000D50 "........" */ + 0x08,0xA4,0x12,0x05,0x02,0x0A,0x08,0x01, /* 00000D58 "........" */ + 0x5B,0x82,0x2C,0x55,0x53,0x42,0x30,0x08, /* 00000D60 "[.,USB0." */ + 0x5F,0x41,0x44,0x52,0x00,0x14,0x20,0x5F, /* 00000D68 "_ADR.. _" */ + 0x50,0x52,0x57,0x00,0xA0,0x10,0x5B,0x12, /* 00000D70 "PRW...[." */ + 0x5F,0x53,0x33,0x5F,0x60,0xA4,0x12,0x06, /* 00000D78 "_S3_`..." */ + 0x02,0x0A,0x0F,0x0A,0x03,0xA1,0x08,0xA4, /* 00000D80 "........" */ + 0x12,0x05,0x02,0x0A,0x0F,0x01,0x5B,0x82, /* 00000D88 "......[." */ + 0x2C,0x55,0x53,0x42,0x31,0x08,0x5F,0x41, /* 00000D90 ",USB1._A" */ + 0x44,0x52,0x01,0x14,0x20,0x5F,0x50,0x52, /* 00000D98 "DR.. _PR" */ + 0x57,0x00,0xA0,0x10,0x5B,0x12,0x5F,0x53, /* 00000DA0 "W...[._S" */ + 0x33,0x5F,0x60,0xA4,0x12,0x06,0x02,0x0A, /* 00000DA8 "3_`....." */ + 0x0F,0x0A,0x03,0xA1,0x08,0xA4,0x12,0x05, /* 00000DB0 "........" */ + 0x02,0x0A,0x0F,0x01,0x08,0x41,0x50,0x49, /* 00000DB8 ".....API" */ + 0x43,0x12,0x41,0x09,0x0C,0x12,0x09,0x04, /* 00000DC0 "C.A....." */ + 0x0B,0xFF,0xFF,0x00,0x00,0x0A,0x10,0x12, /* 00000DC8 "........" */ + 0x09,0x04,0x0B,0xFF,0xFF,0x01,0x00,0x0A, /* 00000DD0 "........" */ + 0x11,0x12,0x0A,0x04,0x0B,0xFF,0xFF,0x0A, /* 00000DD8 "........" */ + 0x02,0x00,0x0A,0x12,0x12,0x0A,0x04,0x0B, /* 00000DE0 "........" */ + 0xFF,0xFF,0x0A,0x03,0x00,0x0A,0x13,0x12, /* 00000DE8 "........" */ + 0x0B,0x04,0x0C,0xFF,0xFF,0x04,0x00,0x00, /* 00000DF0 "........" */ + 0x00,0x0A,0x10,0x12,0x0B,0x04,0x0C,0xFF, /* 00000DF8 "........" */ + 0xFF,0x04,0x00,0x01,0x00,0x0A,0x11,0x12, /* 00000E00 "........" */ + 0x0C,0x04,0x0C,0xFF,0xFF,0x04,0x00,0x0A, /* 00000E08 "........" */ + 0x02,0x00,0x0A,0x12,0x12,0x0C,0x04,0x0C, /* 00000E10 "........" */ + 0xFF,0xFF,0x04,0x00,0x0A,0x03,0x00,0x0A, /* 00000E18 "........" */ + 0x13,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x05, /* 00000E20 "........" */ + 0x00,0x00,0x00,0x0A,0x11,0x12,0x0B,0x04, /* 00000E28 "........" */ + 0x0C,0xFF,0xFF,0x05,0x00,0x01,0x00,0x0A, /* 00000E30 "........" */ + 0x12,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x05, /* 00000E38 "........" */ + 0x00,0x0A,0x02,0x00,0x0A,0x13,0x12,0x0C, /* 00000E40 "........" */ + 0x04,0x0C,0xFF,0xFF,0x05,0x00,0x0A,0x03, /* 00000E48 "........" */ + 0x00,0x0A,0x10,0x08,0x50,0x49,0x43,0x4D, /* 00000E50 "....PICM" */ + 0x12,0x49,0x0A,0x0C,0x12,0x0B,0x04,0x0B, /* 00000E58 ".I......" */ + 0xFF,0xFF,0x00,0x4C,0x4E,0x4B,0x41,0x00, /* 00000E60 "...LNKA." */ + 0x12,0x0B,0x04,0x0B,0xFF,0xFF,0x01,0x4C, /* 00000E68 ".......L" */ + 0x4E,0x4B,0x42,0x00,0x12,0x0C,0x04,0x0B, /* 00000E70 "NKB....." */ + 0xFF,0xFF,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 00000E78 "....LNKC" */ + 0x00,0x12,0x0C,0x04,0x0B,0xFF,0xFF,0x0A, /* 00000E80 "........" */ + 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 00000E88 ".LNKD..." */ + 0x04,0x0C,0xFF,0xFF,0x04,0x00,0x00,0x4C, /* 00000E90 ".......L" */ + 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 00000E98 "NKA....." */ + 0xFF,0xFF,0x04,0x00,0x01,0x4C,0x4E,0x4B, /* 00000EA0 ".....LNK" */ + 0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 00000EA8 "B......." */ + 0x04,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 00000EB0 "....LNKC" */ + 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x04, /* 00000EB8 "........" */ + 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00, /* 00000EC0 "...LNKD." */ + 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x05,0x00, /* 00000EC8 "........" */ + 0x00,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0D, /* 00000ED0 ".LNKB..." */ + 0x04,0x0C,0xFF,0xFF,0x05,0x00,0x01,0x4C, /* 00000ED8 ".......L" */ + 0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C, /* 00000EE0 "NKC....." */ + 0xFF,0xFF,0x05,0x00,0x0A,0x02,0x4C,0x4E, /* 00000EE8 "......LN" */ + 0x4B,0x44,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000EF0 "KD......" */ + 0xFF,0x05,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000EF8 ".....LNK" */ + 0x41,0x00,0x14,0x19,0x5F,0x50,0x52,0x54, /* 00000F00 "A..._PRT" */ + 0x00,0xA0,0x0B,0x92,0x50,0x49,0x43,0x46, /* 00000F08 "....PICF" */ + 0xA4,0x50,0x49,0x43,0x4D,0xA1,0x06,0xA4, /* 00000F10 ".PICM..." */ + 0x41,0x50,0x49,0x43,0x5B,0x82,0x49,0x27, /* 00000F18 "APIC[.I'" */ + 0x50,0x47,0x30,0x41,0x08,0x5F,0x41,0x44, /* 00000F20 "PG0A._AD" */ + 0x52,0x0C,0x00,0x00,0x01,0x00,0x14,0x20, /* 00000F28 "R...... " */ + 0x5F,0x50,0x52,0x57,0x00,0xA0,0x10,0x5B, /* 00000F30 "_PRW...[" */ + 0x12,0x5F,0x53,0x33,0x5F,0x60,0xA4,0x12, /* 00000F38 "._S3_`.." */ + 0x06,0x02,0x0A,0x29,0x0A,0x03,0xA1,0x08, /* 00000F40 "...)...." */ + 0xA4,0x12,0x05,0x02,0x0A,0x29,0x01,0x08, /* 00000F48 ".....).." */ + 0x41,0x50,0x49,0x43,0x12,0x4D,0x0F,0x14, /* 00000F50 "APIC.M.." */ + 0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,0x00, /* 00000F58 "........" */ + 0x00,0x00,0x0A,0x19,0x12,0x0B,0x04,0x0C, /* 00000F60 "........" */ + 0xFF,0xFF,0x01,0x00,0x01,0x00,0x0A,0x1A, /* 00000F68 "........" */ + 0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x01,0x00, /* 00000F70 "........" */ + 0x0A,0x02,0x00,0x0A,0x1B,0x12,0x0C,0x04, /* 00000F78 "........" */ + 0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x03,0x00, /* 00000F80 "........" */ + 0x0A,0x18,0x12,0x0B,0x04,0x0C,0xFF,0xFF, /* 00000F88 "........" */ + 0x03,0x00,0x00,0x00,0x0A,0x19,0x12,0x0B, /* 00000F90 "........" */ + 0x04,0x0C,0xFF,0xFF,0x03,0x00,0x01,0x00, /* 00000F98 "........" */ + 0x0A,0x1A,0x12,0x0C,0x04,0x0C,0xFF,0xFF, /* 00000FA0 "........" */ + 0x03,0x00,0x0A,0x02,0x00,0x0A,0x1B,0x12, /* 00000FA8 "........" */ + 0x0C,0x04,0x0C,0xFF,0xFF,0x03,0x00,0x0A, /* 00000FB0 "........" */ + 0x03,0x00,0x0A,0x18,0x12,0x0B,0x04,0x0C, /* 00000FB8 "........" */ + 0xFF,0xFF,0x04,0x00,0x00,0x00,0x0A,0x1A, /* 00000FC0 "........" */ + 0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x04,0x00, /* 00000FC8 "........" */ + 0x01,0x00,0x0A,0x1B,0x12,0x0C,0x04,0x0C, /* 00000FD0 "........" */ + 0xFF,0xFF,0x04,0x00,0x0A,0x02,0x00,0x0A, /* 00000FD8 "........" */ + 0x18,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x04, /* 00000FE0 "........" */ + 0x00,0x0A,0x03,0x00,0x0A,0x19,0x12,0x0B, /* 00000FE8 "........" */ + 0x04,0x0C,0xFF,0xFF,0x05,0x00,0x00,0x00, /* 00000FF0 "........" */ + 0x0A,0x1B,0x12,0x0B,0x04,0x0C,0xFF,0xFF, /* 00000FF8 "........" */ + 0x05,0x00,0x01,0x00,0x0A,0x18,0x12,0x0C, /* 00001000 "........" */ + 0x04,0x0C,0xFF,0xFF,0x05,0x00,0x0A,0x02, /* 00001008 "........" */ + 0x00,0x0A,0x19,0x12,0x0C,0x04,0x0C,0xFF, /* 00001010 "........" */ + 0xFF,0x05,0x00,0x0A,0x03,0x00,0x0A,0x1A, /* 00001018 "........" */ + 0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x06,0x00, /* 00001020 "........" */ + 0x00,0x00,0x0A,0x18,0x12,0x0B,0x04,0x0C, /* 00001028 "........" */ + 0xFF,0xFF,0x06,0x00,0x01,0x00,0x0A,0x19, /* 00001030 "........" */ + 0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x06,0x00, /* 00001038 "........" */ + 0x0A,0x02,0x00,0x0A,0x1A,0x12,0x0C,0x04, /* 00001040 "........" */ + 0x0C,0xFF,0xFF,0x06,0x00,0x0A,0x03,0x00, /* 00001048 "........" */ + 0x0A,0x1B,0x08,0x50,0x49,0x43,0x4D,0x12, /* 00001050 "...PICM." */ + 0x45,0x12,0x14,0x12,0x0D,0x04,0x0C,0xFF, /* 00001058 "E......." */ + 0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B,0x42, /* 00001060 "....LNKB" */ + 0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x01, /* 00001068 "........" */ + 0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 00001070 "..LNKC.." */ + 0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A, /* 00001078 "........" */ + 0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0E, /* 00001080 ".LNKD..." */ + 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x03, /* 00001088 "........" */ + 0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04, /* 00001090 "LNKA...." */ + 0x0C,0xFF,0xFF,0x03,0x00,0x00,0x4C,0x4E, /* 00001098 "......LN" */ + 0x4B,0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF, /* 000010A0 "KB......" */ + 0xFF,0x03,0x00,0x01,0x4C,0x4E,0x4B,0x43, /* 000010A8 "....LNKC" */ + 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x03, /* 000010B0 "........" */ + 0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00, /* 000010B8 "...LNKD." */ + 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x03,0x00, /* 000010C0 "........" */ + 0x0A,0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12, /* 000010C8 "..LNKA.." */ + 0x0D,0x04,0x0C,0xFF,0xFF,0x04,0x00,0x00, /* 000010D0 "........" */ + 0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04, /* 000010D8 "LNKC...." */ + 0x0C,0xFF,0xFF,0x04,0x00,0x01,0x4C,0x4E, /* 000010E0 "......LN" */ + 0x4B,0x44,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 000010E8 "KD......" */ + 0xFF,0x04,0x00,0x0A,0x02,0x4C,0x4E,0x4B, /* 000010F0 ".....LNK" */ + 0x41,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 000010F8 "A......." */ + 0x04,0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x42, /* 00001100 "....LNKB" */ + 0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x05, /* 00001108 "........" */ + 0x00,0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12, /* 00001110 "..LNKD.." */ + 0x0D,0x04,0x0C,0xFF,0xFF,0x05,0x00,0x01, /* 00001118 "........" */ + 0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0E,0x04, /* 00001120 "LNKA...." */ + 0x0C,0xFF,0xFF,0x05,0x00,0x0A,0x02,0x4C, /* 00001128 ".......L" */ + 0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00001130 "NKB....." */ + 0xFF,0xFF,0x05,0x00,0x0A,0x03,0x4C,0x4E, /* 00001138 "......LN" */ + 0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C,0xFF, /* 00001140 "KC......" */ + 0xFF,0x06,0x00,0x00,0x4C,0x4E,0x4B,0x41, /* 00001148 "....LNKA" */ + 0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x06, /* 00001150 "........" */ + 0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00,0x12, /* 00001158 "..LNKB.." */ + 0x0E,0x04,0x0C,0xFF,0xFF,0x06,0x00,0x0A, /* 00001160 "........" */ + 0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E, /* 00001168 ".LNKC..." */ + 0x04,0x0C,0xFF,0xFF,0x06,0x00,0x0A,0x03, /* 00001170 "........" */ + 0x4C,0x4E,0x4B,0x44,0x00,0x14,0x19,0x5F, /* 00001178 "LNKD..._" */ + 0x50,0x52,0x54,0x00,0xA0,0x0B,0x92,0x50, /* 00001180 "PRT....P" */ + 0x49,0x43,0x46,0xA4,0x50,0x49,0x43,0x4D, /* 00001188 "ICF.PICM" */ + 0xA1,0x06,0xA4,0x41,0x50,0x49,0x43,0x5B, /* 00001190 "...APIC[" */ + 0x82,0x47,0x0C,0x50,0x47,0x30,0x42,0x08, /* 00001198 ".G.PG0B." */ + 0x5F,0x41,0x44,0x52,0x0C,0x00,0x00,0x02, /* 000011A0 "_ADR...." */ + 0x00,0x14,0x20,0x5F,0x50,0x52,0x57,0x00, /* 000011A8 ".. _PRW." */ + 0xA0,0x10,0x5B,0x12,0x5F,0x53,0x33,0x5F, /* 000011B0 "..[._S3_" */ + 0x60,0xA4,0x12,0x06,0x02,0x0A,0x22,0x0A, /* 000011B8 "`....."." */ + 0x03,0xA1,0x08,0xA4,0x12,0x05,0x02,0x0A, /* 000011C0 "........" */ + 0x22,0x01,0x08,0x41,0x50,0x49,0x43,0x12, /* 000011C8 ""..APIC." */ + 0x34,0x04,0x12,0x0B,0x04,0x0C,0xFF,0xFF, /* 000011D0 "4......." */ + 0x01,0x00,0x00,0x00,0x0A,0x1F,0x12,0x0B, /* 000011D8 "........" */ + 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x01,0x00, /* 000011E0 "........" */ + 0x0A,0x20,0x12,0x0C,0x04,0x0C,0xFF,0xFF, /* 000011E8 ". ......" */ + 0x01,0x00,0x0A,0x02,0x00,0x0A,0x21,0x12, /* 000011F0 "......!." */ + 0x0C,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A, /* 000011F8 "........" */ + 0x03,0x00,0x0A,0x22,0x08,0x50,0x49,0x43, /* 00001200 "...".PIC" */ + 0x4D,0x12,0x3C,0x04,0x12,0x0D,0x04,0x0C, /* 00001208 "M.<....." */ + 0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B, /* 00001210 ".....LNK" */ + 0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00001218 "A......." */ + 0x01,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00, /* 00001220 "...LNKB." */ + 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00, /* 00001228 "........" */ + 0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 00001230 "..LNKC.." */ + 0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A, /* 00001238 "........" */ + 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x14,0x19, /* 00001240 ".LNKD..." */ + 0x5F,0x50,0x52,0x54,0x00,0xA0,0x0B,0x92, /* 00001248 "_PRT...." */ + 0x50,0x49,0x43,0x46,0xA4,0x50,0x49,0x43, /* 00001250 "PICF.PIC" */ + 0x4D,0xA1,0x06,0xA4,0x41,0x50,0x49,0x43, /* 00001258 "M...APIC" */ + 0x10,0x49,0x06,0x5F,0x47,0x50,0x45,0x14, /* 00001260 ".I._GPE." */ + 0x13,0x5F,0x4C,0x30,0x38,0x00,0x86,0x5C, /* 00001268 "._L08..\" */ + 0x2E,0x5F,0x53,0x42,0x5F,0x50,0x43,0x49, /* 00001270 "._SB_PCI" */ + 0x31,0x0A,0x02,0x14,0x1C,0x5F,0x4C,0x30, /* 00001278 "1...._L0" */ + 0x46,0x00,0x86,0x5C,0x2F,0x04,0x5F,0x53, /* 00001280 "F..\/._S" */ + 0x42,0x5F,0x50,0x43,0x49,0x31,0x54,0x50, /* 00001288 "B_PCI1TP" */ + 0x32,0x50,0x55,0x53,0x42,0x30,0x0A,0x02, /* 00001290 "2PUSB0.." */ + 0x14,0x18,0x5F,0x4C,0x32,0x32,0x00,0x86, /* 00001298 ".._L22.." */ + 0x5C,0x2F,0x03,0x5F,0x53,0x42,0x5F,0x50, /* 000012A0 "\/._SB_P" */ + 0x43,0x49,0x31,0x50,0x47,0x30,0x42,0x0A, /* 000012A8 "CI1PG0B." */ + 0x02,0x14,0x18,0x5F,0x4C,0x32,0x39,0x00, /* 000012B0 "..._L29." */ + 0x86,0x5C,0x2F,0x03,0x5F,0x53,0x42,0x5F, /* 000012B8 ".\/._SB_" */ + 0x50,0x43,0x49,0x31,0x50,0x47,0x30,0x41, /* 000012C0 "PCI1PG0A" */ + 0x0A,0x02,0x14,0x11,0x5F,0x50,0x54,0x53, /* 000012C8 "...._PTS" */ + 0x01,0x7D,0x68,0x0A,0xF0,0x60,0x70,0x60, /* 000012D0 ".}h..`p`" */ + 0x44,0x42,0x47,0x31,0x08,0x50,0x49,0x43, /* 000012D8 "DBG1.PIC" */ + 0x46,0x00,0x14,0x0C,0x5F,0x50,0x49,0x43, /* 000012E0 "F..._PIC" */ + 0x01,0x70,0x68,0x50,0x49,0x43,0x46,0x5B, /* 000012E8 ".phPICF[" */ + 0x80,0x44,0x45,0x42,0x47,0x01,0x0A,0x80, /* 000012F0 ".DEBG..." */ + 0x01,0x5B,0x81,0x0B,0x44,0x45,0x42,0x47, /* 000012F8 ".[..DEBG" */ + 0x11,0x44,0x42,0x47,0x31,0x08,0x5B,0x80, /* 00001300 ".DBG1.[." */ + 0x45,0x58,0x54,0x4D,0x00,0x0C,0x3C,0xF8, /* 00001308 "EXTM..<." */ + 0x0F,0x00,0x0A,0x04,0x5B,0x81,0x0B,0x45, /* 00001310 "....[..E" */ + 0x58,0x54,0x4D,0x12,0x41,0x4D,0x45,0x4D, /* 00001318 "XTM.AMEM" */ + 0x20,0x5B,0x80,0x56,0x47,0x41,0x4D,0x00, /* 00001320 " [.VGAM." */ + 0x0C,0x02,0x00,0x0C,0x00,0x01,0x5B,0x81, /* 00001328 "......[." */ + 0x0B,0x56,0x47,0x41,0x4D,0x11,0x56,0x47, /* 00001330 ".VGAM.VG" */ + 0x41,0x31,0x08,0x5B,0x80,0x47,0x52,0x41, /* 00001338 "A1.[.GRA" */ + 0x4D,0x00,0x0B,0x00,0x04,0x0B,0x00,0x01, /* 00001340 "M......." */ + 0x5B,0x81,0x0E,0x47,0x52,0x41,0x4D,0x11, /* 00001348 "[..GRAM." */ + 0x00,0x40,0x08,0x46,0x4C,0x47,0x30,0x08, /* 00001350 ".@.FLG0." */ + 0x5B,0x80,0x47,0x53,0x54,0x53,0x01,0x0B, /* 00001358 "[.GSTS.." */ + 0x28,0xC0,0x0A,0x02,0x5B,0x81,0x0D,0x47, /* 00001360 "(...[..G" */ + 0x53,0x54,0x53,0x01,0x00,0x04,0x49,0x52, /* 00001368 "STS...IR" */ + 0x51,0x52,0x01,0x5B,0x80,0x5A,0x30,0x30, /* 00001370 "QR.[.Z00" */ + 0x37,0x01,0x0A,0x21,0x01,0x5B,0x81,0x0B, /* 00001378 "7..!.[.." */ + 0x5A,0x30,0x30,0x37,0x01,0x5A,0x30,0x30, /* 00001380 "Z007.Z00" */ + 0x38,0x08,0x5B,0x80,0x5A,0x30,0x30,0x39, /* 00001388 "8.[.Z009" */ + 0x01,0x0A,0xA1,0x01,0x5B,0x81,0x0B,0x5A, /* 00001390 "....[..Z" */ + 0x30,0x30,0x39,0x01,0x5A,0x30,0x30,0x41, /* 00001398 "009.Z00A" */ + 0x08,0x10,0x45,0x53,0x5F,0x53,0x42,0x5F, /* 000013A0 "..ES_SB_" */ + 0x08,0x4F,0x53,0x54,0x42,0xFF,0x14,0x19, /* 000013A8 ".OSTB..." */ + 0x4F,0x53,0x54,0x50,0x00,0xA0,0x0D,0x93, /* 000013B0 "OSTP...." */ + 0x4F,0x53,0x54,0x42,0xFF,0x70,0x00,0x4F, /* 000013B8 "OSTB.p.O" */ + 0x53,0x54,0x42,0xA4,0x4F,0x53,0x54,0x42, /* 000013C0 "STB.OSTB" */ + 0x14,0x4B,0x05,0x53,0x45,0x51,0x4C,0x0A, /* 000013C8 ".K.SEQL." */ + 0x70,0x87,0x68,0x60,0x70,0x87,0x69,0x61, /* 000013D0 "p.h`p.ia" */ + 0xA0,0x07,0x92,0x93,0x60,0x61,0xA4,0x00, /* 000013D8 "....`a.." */ + 0x08,0x42,0x55,0x46,0x30,0x11,0x02,0x60, /* 000013E0 ".BUF0..`" */ + 0x70,0x68,0x42,0x55,0x46,0x30,0x08,0x42, /* 000013E8 "phBUF0.B" */ + 0x55,0x46,0x31,0x11,0x02,0x60,0x70,0x69, /* 000013F0 "UF1..`pi" */ + 0x42,0x55,0x46,0x31,0x70,0x00,0x62,0xA2, /* 000013F8 "BUF1p.b." */ + 0x22,0x95,0x62,0x60,0x70,0x83,0x88,0x42, /* 00001400 "".b`p..B" */ + 0x55,0x46,0x30,0x62,0x00,0x63,0x70,0x83, /* 00001408 "UF0b.cp." */ + 0x88,0x42,0x55,0x46,0x31,0x62,0x00,0x64, /* 00001410 ".BUF1b.d" */ + 0xA0,0x07,0x92,0x93,0x63,0x64,0xA4,0x00, /* 00001418 "....cd.." */ + 0x75,0x62,0xA4,0x01,0x14,0x16,0x44,0x41, /* 00001420 "ub....DA" */ + 0x44,0x44,0x02,0x70,0x69,0x60,0x70,0x68, /* 00001428 "DD.pi`ph" */ + 0x61,0x72,0x79,0x61,0x0A,0x10,0x00,0x60, /* 00001430 "arya...`" */ + 0x60,0xA4,0x60,0x14,0x25,0x47,0x48,0x43, /* 00001438 "`.`.%GHC" */ + 0x45,0x01,0x70,0x83,0x88,0x5E,0x2E,0x50, /* 00001440 "E.p..^.P" */ + 0x43,0x49,0x30,0x48,0x43,0x4C,0x4B,0x68, /* 00001448 "CI0HCLKh" */ + 0x00,0x61,0xA0,0x0A,0x93,0x7B,0x61,0x01, /* 00001450 ".a...{a." */ + 0x00,0x01,0xA4,0x0A,0x0F,0xA1,0x03,0xA4, /* 00001458 "........" */ + 0x00,0x14,0x26,0x47,0x48,0x43,0x4E,0x01, /* 00001460 "..&GHCN." */ + 0x70,0x00,0x60,0x70,0x83,0x88,0x5E,0x2E, /* 00001468 "p.`p..^." */ + 0x50,0x43,0x49,0x30,0x48,0x43,0x4C,0x4B, /* 00001470 "PCI0HCLK" */ + 0x68,0x00,0x61,0x70,0x7A,0x7B,0x61,0x0A, /* 00001478 "h.apz{a." */ + 0xF0,0x00,0x0A,0x04,0x00,0x60,0xA4,0x60, /* 00001480 ".....`.`" */ + 0x14,0x27,0x47,0x48,0x43,0x4C,0x01,0x70, /* 00001488 ".'GHCL.p" */ + 0x00,0x60,0x70,0x83,0x88,0x5E,0x2E,0x50, /* 00001490 ".`p..^.P" */ + 0x43,0x49,0x30,0x48,0x43,0x4C,0x4B,0x68, /* 00001498 "CI0HCLKh" */ + 0x00,0x61,0x70,0x7A,0x7B,0x61,0x0B,0x00, /* 000014A0 ".apz{a.." */ + 0x0F,0x00,0x0A,0x08,0x00,0x60,0xA4,0x60, /* 000014A8 ".....`.`" */ + 0x14,0x4C,0x05,0x47,0x42,0x55,0x53,0x02, /* 000014B0 ".L.GBUS." */ + 0x70,0x00,0x60,0xA2,0x4F,0x04,0x95,0x60, /* 000014B8 "p.`.O..`" */ + 0x0A,0x04,0x70,0x83,0x88,0x5E,0x2E,0x50, /* 000014C0 "..p..^.P" */ + 0x43,0x49,0x30,0x42,0x55,0x53,0x4E,0x60, /* 000014C8 "CI0BUSN`" */ + 0x00,0x61,0xA0,0x36,0x93,0x7B,0x61,0x0A, /* 000014D0 ".a.6.{a." */ + 0x03,0x00,0x0A,0x03,0xA0,0x2C,0x93,0x68, /* 000014D8 ".....,.h" */ + 0x7A,0x7B,0x61,0x0A,0x70,0x00,0x0A,0x04, /* 000014E0 "z{a.p..." */ + 0x00,0xA0,0x1F,0x91,0x93,0x69,0x0A,0xFF, /* 000014E8 ".....i.." */ + 0x93,0x69,0x7A,0x7B,0x61,0x0B,0x00,0x03, /* 000014F0 ".iz{a..." */ + 0x00,0x0A,0x08,0x00,0xA4,0x7A,0x7B,0x61, /* 000014F8 ".....z{a" */ + 0x0C,0x00,0x00,0xFF,0x00,0x00,0x0A,0x10, /* 00001500 "........" */ + 0x00,0x75,0x60,0xA4,0x00,0x14,0x4B,0x0C, /* 00001508 ".u`...K." */ + 0x47,0x57,0x42,0x4E,0x02,0x08,0x42,0x55, /* 00001510 "GWBN..BU" */ + 0x46,0x30,0x11,0x15,0x0A,0x12,0x88,0x0D, /* 00001518 "F0......" */ + 0x00,0x02,0x0C,0x00,0x00,0x00,0x00,0x00, /* 00001520 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x79,0x00, /* 00001528 "......y." */ + 0x8B,0x42,0x55,0x46,0x30,0x0A,0x08,0x42, /* 00001530 ".BUF0..B" */ + 0x4D,0x49,0x4E,0x8B,0x42,0x55,0x46,0x30, /* 00001538 "MIN.BUF0" */ + 0x0A,0x0A,0x42,0x4D,0x41,0x58,0x8B,0x42, /* 00001540 "..BMAX.B" */ + 0x55,0x46,0x30,0x0A,0x0E,0x42,0x4C,0x45, /* 00001548 "UF0..BLE" */ + 0x4E,0x70,0x00,0x60,0xA2,0x4B,0x07,0x95, /* 00001550 "Np.`.K.." */ + 0x60,0x0A,0x04,0x70,0x83,0x88,0x5E,0x2E, /* 00001558 "`..p..^." */ + 0x50,0x43,0x49,0x30,0x42,0x55,0x53,0x4E, /* 00001560 "PCI0BUSN" */ + 0x60,0x00,0x61,0xA0,0x42,0x06,0x93,0x7B, /* 00001568 "`.a.B..{" */ + 0x61,0x0A,0x03,0x00,0x0A,0x03,0xA0,0x47, /* 00001570 "a......G" */ + 0x05,0x93,0x68,0x7A,0x7B,0x61,0x0A,0x70, /* 00001578 "..hz{a.p" */ + 0x00,0x0A,0x04,0x00,0xA0,0x49,0x04,0x91, /* 00001580 ".....I.." */ + 0x93,0x69,0x0A,0xFF,0x93,0x69,0x7A,0x7B, /* 00001588 ".i...iz{" */ + 0x61,0x0B,0x00,0x03,0x00,0x0A,0x08,0x00, /* 00001590 "a......." */ + 0x70,0x7A,0x7B,0x61,0x0C,0x00,0x00,0xFF, /* 00001598 "pz{a...." */ + 0x00,0x00,0x0A,0x10,0x00,0x42,0x4D,0x49, /* 000015A0 ".....BMI" */ + 0x4E,0x70,0x7A,0x61,0x0A,0x18,0x00,0x42, /* 000015A8 "Npza...B" */ + 0x4D,0x41,0x58,0x74,0x42,0x4D,0x41,0x58, /* 000015B0 "MAXtBMAX" */ + 0x42,0x4D,0x49,0x4E,0x42,0x4C,0x45,0x4E, /* 000015B8 "BMINBLEN" */ + 0x75,0x42,0x4C,0x45,0x4E,0xA4,0x52,0x54, /* 000015C0 "uBLEN.RT" */ + 0x41,0x47,0x42,0x55,0x46,0x30,0x75,0x60, /* 000015C8 "AGBUF0u`" */ + 0xA4,0x52,0x54,0x41,0x47,0x42,0x55,0x46, /* 000015D0 ".RTAGBUF" */ + 0x30,0x14,0x48,0x14,0x47,0x4D,0x45,0x4D, /* 000015D8 "0.H.GMEM" */ + 0x02,0x08,0x42,0x55,0x46,0x30,0x11,0x1F, /* 000015E0 "..BUF0.." */ + 0x0A,0x1C,0x87,0x17,0x00,0x00,0x0C,0x01, /* 000015E8 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 000015F0 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 000015F8 "........" */ + 0x00,0x00,0x00,0x00,0x79,0x00,0x8A,0x42, /* 00001600 "....y..B" */ + 0x55,0x46,0x30,0x0A,0x0A,0x4D,0x4D,0x49, /* 00001608 "UF0..MMI" */ + 0x4E,0x8A,0x42,0x55,0x46,0x30,0x0A,0x0E, /* 00001610 "N.BUF0.." */ + 0x4D,0x4D,0x41,0x58,0x8A,0x42,0x55,0x46, /* 00001618 "MMAX.BUF" */ + 0x30,0x0A,0x16,0x4D,0x4C,0x45,0x4E,0x70, /* 00001620 "0..MLENp" */ + 0x00,0x60,0x70,0x00,0x64,0x70,0x00,0x63, /* 00001628 ".`p.dp.c" */ + 0xA2,0x45,0x0E,0x95,0x60,0x0A,0x10,0x70, /* 00001630 ".E..`..p" */ + 0x83,0x88,0x5E,0x2E,0x50,0x43,0x49,0x30, /* 00001638 "..^.PCI0" */ + 0x4D,0x4D,0x49,0x4F,0x60,0x00,0x61,0x75, /* 00001640 "MMIO`.au" */ + 0x60,0x70,0x83,0x88,0x5E,0x2E,0x50,0x43, /* 00001648 "`p..^.PC" */ + 0x49,0x30,0x4D,0x4D,0x49,0x4F,0x60,0x00, /* 00001650 "I0MMIO`." */ + 0x62,0xA0,0x4A,0x0B,0x93,0x7B,0x61,0x0A, /* 00001658 "b.J..{a." */ + 0x03,0x00,0x0A,0x03,0xA0,0x4F,0x0A,0x93, /* 00001660 ".....O.." */ + 0x68,0x7B,0x62,0x0A,0x07,0x00,0xA0,0x45, /* 00001668 "h{b....E" */ + 0x0A,0x91,0x93,0x69,0x0A,0xFF,0x93,0x69, /* 00001670 "...i...i" */ + 0x7A,0x7B,0x62,0x0A,0x30,0x00,0x0A,0x04, /* 00001678 "z{b.0..." */ + 0x00,0x70,0x79,0x7B,0x61,0x0C,0x00,0xFF, /* 00001680 ".py{a..." */ + 0xFF,0xFF,0x00,0x0A,0x08,0x00,0x4D,0x4D, /* 00001688 "......MM" */ + 0x49,0x4E,0x70,0x79,0x7B,0x62,0x0C,0x00, /* 00001690 "INpy{b.." */ + 0xFF,0xFF,0xFF,0x00,0x0A,0x08,0x00,0x4D, /* 00001698 ".......M" */ + 0x4D,0x41,0x58,0x7D,0x4D,0x4D,0x41,0x58, /* 000016A0 "MAX}MMAX" */ + 0x0B,0xFF,0xFF,0x4D,0x4D,0x41,0x58,0x74, /* 000016A8 "...MMAXt" */ + 0x4D,0x4D,0x41,0x58,0x4D,0x4D,0x49,0x4E, /* 000016B0 "MMAXMMIN" */ + 0x4D,0x4C,0x45,0x4E,0xA0,0x10,0x64,0x73, /* 000016B8 "MLEN..ds" */ + 0x52,0x54,0x41,0x47,0x42,0x55,0x46,0x30, /* 000016C0 "RTAGBUF0" */ + 0x63,0x65,0x70,0x65,0x63,0xA1,0x44,0x04, /* 000016C8 "cepec.D." */ + 0xA0,0x37,0x91,0x90,0x93,0x69,0x0A,0xFF, /* 000016D0 ".7...i.." */ + 0x93,0x68,0x00,0x93,0x69,0x5E,0x2E,0x50, /* 000016D8 ".h..i^.P" */ + 0x43,0x49,0x30,0x53,0x42,0x4C,0x4B,0x70, /* 000016E0 "CI0SBLKp" */ + 0x5E,0x2E,0x50,0x43,0x49,0x30,0x54,0x4F, /* 000016E8 "^.PCI0TO" */ + 0x4D,0x31,0x4D,0x4D,0x49,0x4E,0x74,0x4D, /* 000016F0 "M1MMINtM" */ + 0x4D,0x41,0x58,0x4D,0x4D,0x49,0x4E,0x4D, /* 000016F8 "MAXMMINM" */ + 0x4C,0x45,0x4E,0x75,0x4D,0x4C,0x45,0x4E, /* 00001700 "LENuMLEN" */ + 0x70,0x52,0x54,0x41,0x47,0x42,0x55,0x46, /* 00001708 "pRTAGBUF" */ + 0x30,0x63,0x75,0x64,0x75,0x60,0xA0,0x09, /* 00001710 "0cudu`.." */ + 0x92,0x64,0x70,0x42,0x55,0x46,0x30,0x63, /* 00001718 ".dpBUF0c" */ + 0xA4,0x63,0x14,0x4B,0x18,0x47,0x49,0x4F, /* 00001720 ".c.K.GIO" */ + 0x52,0x02,0x08,0x42,0x55,0x46,0x30,0x11, /* 00001728 "R..BUF0." */ + 0x1F,0x0A,0x1C,0x87,0x17,0x00,0x01,0x0C, /* 00001730 "........" */ + 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00001738 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00001740 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x79,0x00,0x8A, /* 00001748 ".....y.." */ + 0x42,0x55,0x46,0x30,0x0A,0x0A,0x50,0x4D, /* 00001750 "BUF0..PM" */ + 0x49,0x4E,0x8A,0x42,0x55,0x46,0x30,0x0A, /* 00001758 "IN.BUF0." */ + 0x0E,0x50,0x4D,0x41,0x58,0x8A,0x42,0x55, /* 00001760 ".PMAX.BU" */ + 0x46,0x30,0x0A,0x16,0x50,0x4C,0x45,0x4E, /* 00001768 "F0..PLEN" */ + 0x70,0x00,0x60,0x70,0x00,0x64,0x70,0x00, /* 00001770 "p.`p.dp." */ + 0x63,0xA2,0x44,0x12,0x95,0x60,0x0A,0x08, /* 00001778 "c.D..`.." */ + 0x70,0x83,0x88,0x5E,0x2E,0x50,0x43,0x49, /* 00001780 "p..^.PCI" */ + 0x30,0x50,0x43,0x49,0x4F,0x60,0x00,0x61, /* 00001788 "0PCIO`.a" */ + 0x75,0x60,0x70,0x83,0x88,0x5E,0x2E,0x50, /* 00001790 "u`p..^.P" */ + 0x43,0x49,0x30,0x50,0x43,0x49,0x4F,0x60, /* 00001798 "CI0PCIO`" */ + 0x00,0x62,0xA0,0x49,0x0F,0x93,0x7B,0x61, /* 000017A0 ".b.I..{a" */ + 0x0A,0x03,0x00,0x0A,0x03,0xA0,0x4E,0x0E, /* 000017A8 "......N." */ + 0x93,0x68,0x7B,0x62,0x0A,0x07,0x00,0xA0, /* 000017B0 ".h{b...." */ + 0x44,0x0E,0x91,0x93,0x69,0x0A,0xFF,0x93, /* 000017B8 "D...i..." */ + 0x69,0x7A,0x7B,0x62,0x0A,0x30,0x00,0x0A, /* 000017C0 "iz{b.0.." */ + 0x04,0x00,0x70,0x7B,0x61,0x0C,0x00,0xF0, /* 000017C8 "..p{a..." */ + 0xFF,0x01,0x00,0x50,0x4D,0x49,0x4E,0x70, /* 000017D0 "...PMINp" */ + 0x7B,0x62,0x0C,0x00,0xF0,0xFF,0x01,0x00, /* 000017D8 "{b......" */ + 0x50,0x4D,0x41,0x58,0x7D,0x50,0x4D,0x41, /* 000017E0 "PMAX}PMA" */ + 0x58,0x0B,0xFF,0x0F,0x50,0x4D,0x41,0x58, /* 000017E8 "X...PMAX" */ + 0x74,0x50,0x4D,0x41,0x58,0x50,0x4D,0x49, /* 000017F0 "tPMAXPMI" */ + 0x4E,0x50,0x4C,0x45,0x4E,0x75,0x50,0x4C, /* 000017F8 "NPLENuPL" */ + 0x45,0x4E,0xA0,0x10,0x64,0x73,0x52,0x54, /* 00001800 "EN..dsRT" */ + 0x41,0x47,0x42,0x55,0x46,0x30,0x63,0x65, /* 00001808 "AGBUF0ce" */ + 0x70,0x65,0x63,0xA1,0x46,0x08,0xA0,0x48, /* 00001810 "pec.F..H" */ + 0x04,0x94,0x50,0x4D,0x41,0x58,0x50,0x4D, /* 00001818 "..PMAXPM" */ + 0x49,0x4E,0xA0,0x30,0x91,0x90,0x93,0x69, /* 00001820 "IN.0...i" */ + 0x0A,0xFF,0x93,0x68,0x00,0x93,0x69,0x5E, /* 00001828 "...h..i^" */ + 0x2E,0x50,0x43,0x49,0x30,0x53,0x42,0x4C, /* 00001830 ".PCI0SBL" */ + 0x4B,0x70,0x0B,0x00,0x0D,0x50,0x4D,0x49, /* 00001838 "Kp...PMI" */ + 0x4E,0x74,0x50,0x4D,0x41,0x58,0x50,0x4D, /* 00001840 "NtPMAXPM" */ + 0x49,0x4E,0x50,0x4C,0x45,0x4E,0x75,0x50, /* 00001848 "INPLENuP" */ + 0x4C,0x45,0x4E,0x70,0x52,0x54,0x41,0x47, /* 00001850 "LENpRTAG" */ + 0x42,0x55,0x46,0x30,0x63,0x75,0x64,0xA0, /* 00001858 "BUF0cud." */ + 0x3A,0x7B,0x61,0x0A,0x10,0x00,0x70,0x0B, /* 00001860 ":{a...p." */ + 0xB0,0x03,0x50,0x4D,0x49,0x4E,0x70,0x0B, /* 00001868 "..PMINp." */ + 0xDF,0x03,0x50,0x4D,0x41,0x58,0x70,0x0A, /* 00001870 "..PMAXp." */ + 0x30,0x50,0x4C,0x45,0x4E,0xA0,0x10,0x64, /* 00001878 "0PLEN..d" */ + 0x73,0x52,0x54,0x41,0x47,0x42,0x55,0x46, /* 00001880 "sRTAGBUF" */ + 0x30,0x63,0x65,0x70,0x65,0x63,0xA1,0x0B, /* 00001888 "0cepec.." */ + 0x70,0x52,0x54,0x41,0x47,0x42,0x55,0x46, /* 00001890 "pRTAGBUF" */ + 0x30,0x63,0x75,0x64,0x75,0x60,0xA0,0x0D, /* 00001898 "0cudu`.." */ + 0x92,0x64,0x70,0x52,0x54,0x41,0x47,0x42, /* 000018A0 ".dpRTAGB" */ + 0x55,0x46,0x30,0x63,0xA4,0x63,0x14,0x28, /* 000018A8 "UF0c.c.(" */ + 0x52,0x54,0x41,0x47,0x01,0x70,0x68,0x60, /* 000018B0 "RTAG.ph`" */ + 0x70,0x87,0x60,0x61,0x74,0x61,0x0A,0x02, /* 000018B8 "p.`ata.." */ + 0x61,0x77,0x61,0x0A,0x08,0x61,0x5B,0x13, /* 000018C0 "awa..a[." */ + 0x60,0x00,0x61,0x52,0x45,0x54,0x42,0x70, /* 000018C8 "`.aRETBp" */ + 0x52,0x45,0x54,0x42,0x62,0xA4,0x62, +}; diff --git a/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl b/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl new file mode 100644 index 0000000000..a45560519b --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl @@ -0,0 +1,204 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +//AMD8111 + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} + }) + + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00} + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) + // Update the Device Number according to SBDN + Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) + + Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { + Return (PICM) + } + Else { + Return (APIC) + } + } + + Device (SBC3) + { + /* acpi smbus it should be 0x00040003 if 8131 present */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) + } + OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) + Field (PIRQ, ByteAcc, Lock, Preserve) + { + PIBA, 8, + PIDC, 8 + } +/* + OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) + Field (TS3_, DWordAcc, NoLock, Preserve) + { + PTS3, 16 + } +*/ + } + + Device (HPET) + { + Name (HPT, 0x00) + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + Return (BUF0) + } + } + + Include ("amd8111_pic.asl") + + Include ("amd8111_isa.asl") + + Device (TP2P) + { + /* 8111 P2P and it should 0x00030000 when 8131 present*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) } + Else { Return (Package (0x02) { 0x08, 0x01 }) } + } + + Device (USB0) + { + Name (_ADR, 0x00000000) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Device (USB1) + { + Name (_ADR, 0x00000001) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Name (APIC, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } + }) + + Name (PICM, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }, + + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }, + + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 } + }) + + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + diff --git a/src/mainboard/amd/serengeti_leopard/dx/amd8111_isa.asl b/src/mainboard/amd/serengeti_leopard/dx/amd8111_isa.asl new file mode 100644 index 0000000000..2b33d7f785 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/amd8111_isa.asl @@ -0,0 +1,208 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +//AMD8111 isa + + Device (ISA) + { + /* lpc 0x00040000 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) + } + + OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers + Field (PIRY, ByteAcc, NoLock, Preserve) + { + Z000, 2, // Parallel Port Range + , 1, + ECP, 1, // ECP Enable + FDC1, 1, // Floppy Drive Controller 1 + FDC2, 1, // Floppy Drive Controller 2 + Offset (0x01), + Z001, 3, // Serial Port A Range + SAEN, 1, // Serial Post A Enabled + Z002, 3, // Serial Port B Range + SBEN, 1 // Serial Post B Enabled + } + + Device (PIC) + { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) + IRQ (Edge, ActiveHigh, Exclusive) {2} + }) + } + + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer16) {4} + }) + } + + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) + IRQ (Edge, ActiveHigh, Exclusive) {0} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) + IRQ (Edge, ActiveHigh, Exclusive) {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) + }) + } + + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) + IRQ (Edge, ActiveHigh, Exclusive) {13} + }) + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x00) + Name (SYR1, ResourceTemplate () + { + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) + IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) + IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + }) + Method (_CRS, 0, NotSerialized) + { + Return (SYR1) + } + } + + Device (MEM) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF + Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404 + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + }) + // Read the Video Memory length + CreateDWordField (BUF0, 0x14, CLEN) + CreateDWordField (BUF0, 0x10, CBAS) + + ShiftLeft (VGA1, 0x09, Local0) + Store (Local0, CLEN) + + Return (BUF0) + } + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Method (_STA, 0, NotSerialized) + { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { Return (0x0F) } + Else { Return (0x00) } + } + } + + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + Include ("superio.asl") + + } + diff --git a/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl b/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl new file mode 100644 index 0000000000..57584b2fe5 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl @@ -0,0 +1,392 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +//AMD8111 pic LNKA B C D + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { // Routing enable + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA) + Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA) + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA) + ShiftLeft (Local1, 0x04, Local1) + Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA) + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC) + Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC) + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC) + ShiftLeft (Local1, 0x04, Local1) + Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC) + } + } + + diff --git a/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl b/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl new file mode 100644 index 0000000000..6a98c8f136 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl @@ -0,0 +1,142 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +//8131 + + Device (PG0A) + { + Name (_ADR, 0x00010000) /* 8132 pcix bridge*/ + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x14) + { + // Slot A - PIRQ BCDA + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, + + //Cypress Slot A - PIRQ BCDA + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, + + //Cypress Slot B - PIRQ CDAB + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, + + //Cypress Slot C - PIRQ DABC + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, + + //Cypress Slot D - PIRQ ABCD + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } + }) + Name (PICM, Package (0x14) + { + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }, + + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }, + + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 }, + + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 }, + + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + Name (_ADR, 0x00020000) /* 8132 pcix bridge 2 */ + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { + // Slot A - PIRQ ABCD + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl b/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl new file mode 100644 index 0000000000..b94c36ffd6 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl @@ -0,0 +1,61 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +// AMD8151 + Device (AGPB) + { + Name (_ADR, 0x00020000) + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + diff --git a/src/mainboard/amd/serengeti_leopard/dx/amdk8_util.asl b/src/mainboard/amd/serengeti_leopard/dx/amdk8_util.asl new file mode 100644 index 0000000000..aeba06675e --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/amdk8_util.asl @@ -0,0 +1,338 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + + +//AMD k8 util for BUSB and res range + + Scope (\_SB) + { + + Name (OSTB, Ones) + Method (OSTP, 0, NotSerialized) + { + If (LEqual (^OSTB, Ones)) + { + Store (0x00, ^OSTB) + } + + Return (^OSTB) + } + + Method (SEQL, 2, Serialized) + { + Store (SizeOf (Arg0), Local0) + Store (SizeOf (Arg1), Local1) + If (LNot (LEqual (Local0, Local1))) { Return (Zero) } + + Name (BUF0, Buffer (Local0) {}) + Store (Arg0, BUF0) + Name (BUF1, Buffer (Local0) {}) + Store (Arg1, BUF1) + Store (Zero, Local2) + While (LLess (Local2, Local0)) + { + Store (DerefOf (Index (BUF0, Local2)), Local3) + Store (DerefOf (Index (BUF1, Local2)), Local4) + If (LNot (LEqual (Local3, Local4))) { Return (Zero) } + + Increment (Local2) + } + + Return (One) + } + + + Method (DADD, 2, NotSerialized) + { + Store( Arg1, Local0) + Store( Arg0, Local1) + Add( ShiftLeft(Local1,16), Local0, Local0) + Return (Local0) + } + + + Method (GHCE, 1, NotSerialized) + { + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + Else { Return (0x00) } + } + + Method (GHCN, 1, NotSerialized) + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) + Return (Local0) + } + + Method (GHCL, 1, NotSerialized) + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) + Return (Local0) + } + + Method (GBUS, 2, NotSerialized) + { + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) + } + } + } + + Increment (Local0) + } + + Return (0x00) + } + + Method (GWBN, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0000, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0000,,,) + }) + CreateWordField (BUF0, 0x08, BMIN) + CreateWordField (BUF0, 0x0A, BMAX) + CreateWordField (BUF0, 0x0E, BLEN) + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) + Store (ShiftRight (Local1, 0x18), BMAX) + Subtract (BMAX, BMIN, BLEN) + Increment (BLEN) + Return (RTAG (BUF0)) + } + } + } + + Increment (Local0) + } + + Return (RTAG (BUF0)) + } + + Method (GMEM, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, MMIN) + CreateDWordField (BUF0, 0x0E, MMAX) + CreateDWordField (BUF0, 0x16, MLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x10)) + { + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) + Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) + Or (MMAX, 0xFFFF, MMAX) + Subtract (MMAX, MMIN, MLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (\_SB.PCI0.TOM1, MMIN) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + } + + Store (RTAG (BUF0), Local3) + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (BUF0, Local3) + } + + Return (Local3) + } + + Method (GIOR, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, PMIN) + CreateDWordField (BUF0, 0x0E, PMAX) + CreateDWordField (BUF0, 0x16, PLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x08)) + { + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (And (Local1, 0x01FFF000), PMIN) + Store (And (Local2, 0x01FFF000), PMAX) + Or (PMAX, 0x0FFF, PMAX) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LGreater (PMAX, PMIN)) + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (0x0D00, PMIN) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + } + + Store (RTAG (BUF0), Local3) + Increment (Local4) + } + + If (And (Local1, 0x10)) + { + Store (0x03B0, PMIN) + Store (0x03DF, PMAX) + Store (0x30, PLEN) + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + } + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (RTAG (BUF0), Local3) + } + + Return (Local3) + } + + Method (RTAG, 1, NotSerialized) + { + Store (Arg0, Local0) + Store (SizeOf (Local0), Local1) + Subtract (Local1, 0x02, Local1) + Multiply (Local1, 0x08, Local1) + CreateField (Local0, 0x00, Local1, RETB) + Store (RETB, Local2) + Return (Local2) + } + } + diff --git a/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl b/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl new file mode 100644 index 0000000000..de39a365c8 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl @@ -0,0 +1,305 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_PR) + { + Processor (CPU0, 0x00, 0x0000C010, 0x06) {} + Processor (CPU1, 0x01, 0x00000000, 0x00) {} + Processor (CPU2, 0x02, 0x00000000, 0x00) {} + Processor (CPU3, 0x03, 0x00000000, 0x00) {} + + } + + Method (FWSO, 0, NotSerialized) { } + + Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) + Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 }) + Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 }) + Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 }) + + Scope (_SB) + { + Device (PCI0) + { + /* BUS0 root bus */ + +/* +//hardcode begin + Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 }) + Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 }) + Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 }) + Name (SBLK, 0x00) + Name (TOM1, 0x40000000) + + // for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4 + // PCI1 must be SBLK Chain + // If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4, + // in acpi_tables.c you can link those SSDT to RSDT according to it's presence. + // Otherwise put the PCI2, PCI3, PCI4 in this dsdt + Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn + + Name (SBDN, 3) // 8111 UnitID Base +//hardcode end +*/ + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_UID, 0x01) + Name (_BBN, 0) + + + // define L1IC Link1 on node0 init completed, so node1 is installed + // We must make sure our bus is 0 ? + OperationRegion (LDT1, PCI_Config, 0xA4, 0x01) + Field (LDT1, ByteAcc, Lock, Preserve) + { + , 5, + L1IC, 1 + } + + } + + Device (PCI1) + { + // BUS 1 first HT Chain + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) // Fake + Name (_UID, 0x02) + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (0x00, \_SB.PCI0.SBLK)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + \_SB.OSTP () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + Include ("pci1_hc.asl") + + } +/* + Device (PCI2) + { + + // BUS ? Second HT Chain + Name (HCIN, 0x01) // HC2 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00180000)) + } + Name (_UID, 0x03) + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci2_hc.asl") + } +*/ + + } + + Scope (_GPE) + { + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI1, 0x02) //PME# Wakeup + } + + Method (_L0F, 0, NotSerialized) + { + Notify (\_SB.PCI1.TP2P.USB0, 0x02) //USB Wakeup + } + + Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B + { + Notify (\_SB.PCI1.PG0B, 0x02) + } + + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + { + Notify (\_SB.PCI1.PG0A, 0x02) + } + } + + Method (_PTS, 1, NotSerialized) + { + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) + } +/* + Method (_WAK, 1, NotSerialized) + { + Or (Arg0, 0xE0, Local0) + Store (Local0, DBG1) + } +*/ + Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode + Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method + { + Store (Arg0, PICF) + } + + OperationRegion (DEBG, SystemIO, 0x80, 0x01) + Field (DEBG, ByteAcc, Lock, Preserve) + { + DBG1, 8 + } + + OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) + Field (EXTM, WordAcc, Lock, Preserve) + { + AMEM, 32 + } + + OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) + Field (VGAM, ByteAcc, Lock, Preserve) + { + VGA1, 8 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + OperationRegion (GSTS, SystemIO, 0xC028, 0x02) + Field (GSTS, ByteAcc, NoLock, Preserve) + { + , 4, + IRQR, 1 + } + + OperationRegion (Z007, SystemIO, 0x21, 0x01) + Field (Z007, ByteAcc, NoLock, Preserve) + { + Z008, 8 + } + + OperationRegion (Z009, SystemIO, 0xA1, 0x01) + Field (Z009, ByteAcc, NoLock, Preserve) + { + Z00A, 8 + } + + Include ("amdk8_util.asl") + +} + diff --git a/src/mainboard/amd/serengeti_leopard/dx/pci1_hc.asl b/src/mainboard/amd/serengeti_leopard/dx/pci1_hc.asl new file mode 100644 index 0000000000..8730387424 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/pci1_hc.asl @@ -0,0 +1,38 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + + Include ("amd8111.asl") //real SB at first + Include ("amd8131.asl") diff --git a/src/mainboard/amd/serengeti_leopard/dx/pci2.asl b/src/mainboard/amd/serengeti_leopard/dx/pci2.asl new file mode 100644 index 0000000000..c1be5d0d4c --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/pci2.asl @@ -0,0 +1,100 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI1.LNKA, DeviceObj) + External (\_SB.PCI1.LNKB, DeviceObj) + External (\_SB.PCI1.LNKC, DeviceObj) + External (\_SB.PCI1.LNKD, DeviceObj) + + + Device (PCI2) + { + + // BUS ? Second HT Chain + Name (HCIN, 0x01) // HC2 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00180000)) + } + + Name (_UID, 0x03) + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci2_hc.asl") + } + } + +} + diff --git a/src/mainboard/amd/serengeti_leopard/dx/pci2_hc.asl b/src/mainboard/amd/serengeti_leopard/dx/pci2_hc.asl new file mode 100644 index 0000000000..d282e71b85 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/pci2_hc.asl @@ -0,0 +1,37 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + + Include ("amd8151.asl") diff --git a/src/mainboard/amd/serengeti_leopard/dx/superio.asl b/src/mainboard/amd/serengeti_leopard/dx/superio.asl new file mode 100644 index 0000000000..ab23dc85e3 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/dx/superio.asl @@ -0,0 +1,37 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +// Include ("w83627hf.asl") diff --git a/src/mainboard/amd/serengeti_leopard/fadt.c b/src/mainboard/amd/serengeti_leopard/fadt.c new file mode 100644 index 0000000000..1ab52c19b5 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/fadt.c @@ -0,0 +1,185 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org> + */ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> + +extern unsigned pm_base; /* pm_base should be set in sb acpi */ + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + + acpi_header_t *header=&(fadt->header); + + printk_debug("pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id,OEM_ID,6); + memcpy(header->oem_table_id,"LXBACPI ",8); + memcpy(header->asl_compiler_id,ASLC,4); + header->asl_compiler_revision=0; + + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt= (u32)dsdt; + fadt->res1=0x0; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile=0x03; + fadt->sci_int=9; + // disable system management mode by setting to 0: + fadt->smi_cmd = 0;//pm_base+0x2f; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pm_base; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = pm_base+0x04; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = pm_base+0x08; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 8; + fadt->gpe1_base = 16; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; // 0x7d these have to be + fadt->mon_alrm = 0; // 0x7e added to cmos.layout + fadt->century = 0; // 0x7f to make rtc alrm work + fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->flags = 0x25; + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pm_base; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pm_base+4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pm_base+0x08; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pm_base+0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = pm_base+0xb0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/serengeti_leopard/failover.c b/src/mainboard/amd/serengeti_leopard/failover.c new file mode 100644 index 0000000000..a1ea247c63 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/failover.c @@ -0,0 +1,126 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/mc146818rtc_early.c" +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +#if CONFIG_LOGICAL_CPUS==1 +#include "cpu/amd/dualcore/dualcore_id.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + +static unsigned long main(unsigned long bist) +{ +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + /* Make cerain my local apic is useable */ +// enable_lapic(); + +#if CONFIG_LOGICAL_CPUS==1 + id = get_node_core_id_x(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(id.nodeid)) { +#else +// nodeid = lapicid() & 0xf; + nodeid = get_node_id(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(nodeid)) { +#endif + /* Is this a cpu only reset? */ + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + /* Is this a secondary cpu? */ + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: +#if 0 + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); +#endif + fallback_image: + return bist; +} diff --git a/src/mainboard/amd/serengeti_leopard/get_bus_conf.c b/src/mainboard/amd/serengeti_leopard/get_bus_conf.c new file mode 100644 index 0000000000..651f64c095 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/get_bus_conf.c @@ -0,0 +1,167 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif + + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +//busnum is default +unsigned char bus_isa = 7 ; +unsigned char bus_8132_0 = 1; +unsigned char bus_8132_1 = 2; +unsigned char bus_8132_2 = 3; +unsigned char bus_8111_0 = 1; +unsigned char bus_8111_1 = 4; +unsigned char bus_8151_0 = 5; +unsigned char bus_8151_1 = 6; +unsigned apicid_8111 ; +unsigned apicid_8132_1; +unsigned apicid_8132_2; + +unsigned sblk; +unsigned pci1234[] = +{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 +}; +unsigned hc_possible_num; +unsigned sbdn; + +static unsigned get_sbdn(void) +{ + device_t dev; + unsigned sbdn = 3;// 8111 unit id base is 3 if 8131 before it + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI , 0); //FIXME: if 8111 PCI is disabled? + if(dev) { + sbdn = (dev->path.u.pci.devfn >> 3) & 0x1f; + } + + return sbdn; +} + +extern void get_sblk_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + + device_t dev; + + if(get_bus_conf_done==1) return; //do it only once + + get_bus_conf_done = 1; + + hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + + get_sblk_pci1234(); + + sbdn = get_sbdn(); + +// bus_8132_0 = node_link_to_bus(0, sblk); + bus_8132_0 = (pci1234[0] >> 16) & 0xff; + bus_8111_0 = bus_8132_0; + + /* 8111 */ + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); + } + else { + printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); + } + + /* 8132-1 */ + dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8132_0); + } + + /* 8132-2 */ + dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8132_0); + } + + /* HT chain 1 */ + if((pci1234[1] & 0x1) == 1) { +// bus_8151_0 = node_link_to_bus( (pci1234[1]>>4) & 0xf, (pci1234[1]>>8) & 0xf); + bus_8151_0 = (pci1234[1] >> 16) & 0xff; + /* 8151 */ + dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +// printk_debug("bus_8151_1=%d\n",bus_8151_1); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_8111 = apicid_base+0; + apicid_8132_1 = apicid_base+1; + apicid_8132_2 = apicid_base+2; +} diff --git a/src/mainboard/amd/serengeti_leopard/irq_tables.c b/src/mainboard/amd/serengeti_leopard/irq_tables.c new file mode 100644 index 0000000000..7eb6c53867 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/irq_tables.c @@ -0,0 +1,163 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*11, /* there can be total 11 devices on the bus */ + 3, /* Where the interrupt router lies (bus) */ + (4<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x42, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, + {0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, + {0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0}, + {0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, + {0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, + {0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, + {0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, + {0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, + {0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + {0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + } +}; + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern unsigned char bus_8132_0; +extern unsigned char bus_8132_1; +extern unsigned char bus_8132_2; +extern unsigned char bus_8111_0; +extern unsigned char bus_8111_1; +extern unsigned char bus_8151_0; +extern unsigned char bus_8151_1; + +extern void get_bus_conf(void); + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + + uint8_t sum=0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_8111_0; + pirq->rtr_devfn = (4<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1022; + pirq->rtr_device = 0x746b; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; +//pci bridge + write_pirq_info(pirq_info, bus_8111_0, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; +//pcix bridge +// write_pirq_info(pirq_info, bus_8132_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++; +//agp bridge + write_pirq_info(pirq_info, bus_8151_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + + return (unsigned long) pirq_info; + +} diff --git a/src/mainboard/amd/serengeti_leopard/mainboard.c b/src/mainboard/amd/serengeti_leopard/mainboard.c new file mode 100644 index 0000000000..9c95128799 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/mainboard.c @@ -0,0 +1,48 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +#if CONFIG_CHIP_NAME == 1 +struct chip_operations mainboard_amd_serengeti_leopard_ops = { + CHIP_NAME("AMD serengeti_leopard mainboard") +}; +#endif diff --git a/src/mainboard/amd/serengeti_leopard/mptable.c b/src/mainboard/amd/serengeti_leopard/mptable.c new file mode 100644 index 0000000000..af0e85f3b9 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/mptable.c @@ -0,0 +1,183 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif + +extern unsigned char bus_isa; +extern unsigned char bus_8132_0; +extern unsigned char bus_8132_1; +extern unsigned char bus_8132_2; +extern unsigned char bus_8111_0; +extern unsigned char bus_8111_1; +extern unsigned char bus_8151_0; +extern unsigned char bus_8151_1; +extern unsigned apicid_8111; +extern unsigned apicid_8132_1; +extern unsigned apicid_8132_2; + +extern void get_bus_conf(void); + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "AMD "; + static const char productid[12] = "SERENGETI_LE"; + struct mp_config_table *mc; + + unsigned char bus_num; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + +/*Bus: Bus ID Type*/ + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); //8111 + { + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8132_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8132_2, 0x11, res->base); + } + } + } + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, apicid_8111, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_8111, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); +//??? What + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (4<<2)|3, apicid_8111, 0x13); +// Onboard AMD USB + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); + +// Slot AGP + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x11); + +//Slot 3 PCI 32 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|2, apicid_8111, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|3, apicid_8111, 0x10); // + +//Slot 4 PCI 32 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); // + +//Slot 1 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|0, apicid_8132_2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|1, apicid_8132_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|2, apicid_8132_2, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|3, apicid_8132_2, 0x3); // + +//Slot 2 PCI-X 133/100/66 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|0, apicid_8132_1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|1, apicid_8132_1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|2, apicid_8132_1, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|3, apicid_8132_1, 0x0);// + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/serengeti_leopard/readme_acpi.txt b/src/mainboard/amd/serengeti_leopard/readme_acpi.txt new file mode 100644 index 0000000000..5419413f1b --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/readme_acpi.txt @@ -0,0 +1,65 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + + + +At this time, For acpi support We got +1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c) +2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_leopard/acpi_tables.c) +3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_leopard/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c) +4. Chipset support: amd8111, amd8132 + +The developers need to change for different MB + +Change dx/dsdt_lb.dsl, according to MB layout + pci1, pci2, pci3, pci4, ...., pci8 + if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c + +Change acpi_tables.c + sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now. + if there is HT-IO board, need to adjust SSDTX_NUM...., ans preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed + +Regarding pci bridge apic and pic + need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c + +About other chipsets, need to develop their special asl such as + ck804.asl --- NB ck804 + bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000 + +yhlu + +09/18/2005 + diff --git a/src/mainboard/amd/serengeti_leopard/reset.c b/src/mainboard/amd/serengeti_leopard/reset.c new file mode 100644 index 0000000000..3db3956ec6 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/reset.c @@ -0,0 +1,6 @@ +#include "../../../southbridge/amd/amd8111/amd8111_reset.c" + +void hard_reset(void) +{ + amd8111_hard_reset(0, 0); +} diff --git a/src/mainboard/amd/serengeti_leopard/resourcemap.c b/src/mainboard/amd/serengeti_leopard/resourcemap.c new file mode 100644 index 0000000000..467520f882 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/resourcemap.c @@ -0,0 +1,265 @@ +/* + * AMD serengeti_leopard needs a different resource map + * + */ + +static void setup_serengeti_leopard_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1 + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + }; + + int max; + max = sizeof(register_values)/sizeof(register_values[0]); + setup_resource_map(register_values, max); +} + diff --git a/src/mainboard/amd/serengeti_leopard/ssdt.c b/src/mainboard/amd/serengeti_leopard/ssdt.c new file mode 100644 index 0000000000..2882194e8c --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/ssdt.c @@ -0,0 +1,81 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +/* + * + * Compilation of "ssdt_lb_x.dsl" - Sat Sep 17 21:31:39 2005 + * + */ +unsigned char AmlCode_ssdt[] = +{ + 0x53,0x53,0x44,0x54,0x21,0x01,0x00,0x00, /* 00000000 "SSDT!..." */ + 0x01,0x0B,0x41,0x4D,0x44,0x2D,0x4B,0x38, /* 00000008 "..AMD-K8" */ + 0x41,0x4D,0x44,0x2D,0x41,0x43,0x50,0x49, /* 00000010 "AMD-ACPI" */ + 0x00,0x00,0x04,0x06,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ + 0x09,0x03,0x05,0x20,0x10,0x4C,0x0F,0x5C, /* 00000020 "... .L.\" */ + 0x2E,0x5F,0x53,0x42,0x5F,0x50,0x43,0x49, /* 00000028 "._SB_PCI" */ + 0x30,0x08,0x42,0x55,0x53,0x4E,0x12,0x16, /* 00000030 "0.BUSN.." */ + 0x04,0x0C,0x11,0x11,0x11,0x11,0x0C,0x22, /* 00000038 "......."" */ + 0x22,0x22,0x22,0x0C,0x33,0x33,0x33,0x33, /* 00000040 """".3333" */ + 0x0C,0x44,0x44,0x44,0x44,0x08,0x4D,0x4D, /* 00000048 ".DDDD.MM" */ + 0x49,0x4F,0x12,0x43,0x05,0x10,0x0C,0x11, /* 00000050 "IO.C...." */ + 0x11,0x11,0x11,0x0C,0x22,0x22,0x22,0x22, /* 00000058 "....""""" */ + 0x0C,0x33,0x33,0x33,0x33,0x0C,0x44,0x44, /* 00000060 ".3333.DD" */ + 0x44,0x44,0x0C,0x55,0x55,0x55,0x55,0x0C, /* 00000068 "DD.UUUU." */ + 0x66,0x66,0x66,0x66,0x0C,0x77,0x77,0x77, /* 00000070 "ffff.www" */ + 0x77,0x0C,0x88,0x88,0x88,0x88,0x0C,0x99, /* 00000078 "w......." */ + 0x99,0x99,0x99,0x0C,0xAA,0xAA,0xAA,0xAA, /* 00000080 "........" */ + 0x0C,0xBB,0xBB,0xBB,0xBB,0x0C,0xCC,0xCC, /* 00000088 "........" */ + 0xCC,0xCC,0x0C,0xDD,0xDD,0xDD,0xDD,0x0C, /* 00000090 "........" */ + 0xEE,0xEE,0xEE,0xEE,0x0C,0x11,0x11,0x11, /* 00000098 "........" */ + 0x11,0x0C,0x22,0x22,0x22,0x22,0x08,0x50, /* 000000A0 ".."""".P" */ + 0x43,0x49,0x4F,0x12,0x2A,0x08,0x0C,0x77, /* 000000A8 "CIO.*..w" */ + 0x77,0x77,0x77,0x0C,0x88,0x88,0x88,0x88, /* 000000B0 "www....." */ + 0x0C,0x99,0x99,0x99,0x99,0x0C,0xAA,0xAA, /* 000000B8 "........" */ + 0xAA,0xAA,0x0C,0xBB,0xBB,0xBB,0xBB,0x0C, /* 000000C0 "........" */ + 0xCC,0xCC,0xCC,0xCC,0x0C,0xDD,0xDD,0xDD, /* 000000C8 "........" */ + 0xDD,0x0C,0xEE,0xEE,0xEE,0xEE,0x08,0x53, /* 000000D0 ".......S" */ + 0x42,0x4C,0x4B,0x0A,0x11,0x08,0x54,0x4F, /* 000000D8 "BLK...TO" */ + 0x4D,0x31,0x0C,0xAA,0xAA,0xAA,0xAA,0x08, /* 000000E0 "M1......" */ + 0x53,0x42,0x44,0x4E,0x0C,0xBB,0xBB,0xBB, /* 000000E8 "SBDN...." */ + 0xBB,0x08,0x48,0x43,0x4C,0x4B,0x12,0x2A, /* 000000F0 "..HCLK.*" */ + 0x08,0x0C,0x11,0x11,0x11,0x11,0x0C,0x22, /* 000000F8 "......."" */ + 0x22,0x22,0x22,0x0C,0x33,0x33,0x33,0x33, /* 00000100 """".3333" */ + 0x0C,0x44,0x44,0x44,0x44,0x0C,0x55,0x55, /* 00000108 ".DDDD.UU" */ + 0x55,0x55,0x0C,0x66,0x66,0x66,0x66,0x0C, /* 00000110 "UU.ffff." */ + 0x77,0x77,0x77,0x77,0x0C,0x88,0x88,0x88, /* 00000118 "wwww...." */ + 0x88, +}; diff --git a/src/mainboard/amd/serengeti_leopard/ssdt2.c b/src/mainboard/amd/serengeti_leopard/ssdt2.c new file mode 100644 index 0000000000..1593519ca1 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/ssdt2.c @@ -0,0 +1,99 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +/* + * + * Compilation of "pci2.asl" - Sat Sep 17 23:31:28 2005 + * + */ +unsigned char AmlCode_ssdt2[] = +{ + 0x53,0x53,0x44,0x54,0xB7,0x01,0x00,0x00, /* 00000000 "SSDT...." */ + 0x01,0xD8,0x41,0x4D,0x44,0x2D,0x4B,0x38, /* 00000008 "..AMD-K8" */ + 0x41,0x4D,0x44,0x41,0x43,0x50,0x49,0x00, /* 00000010 "AMDACPI." */ + 0x00,0x00,0x04,0x06,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ + 0x09,0x03,0x05,0x20,0x10,0x42,0x19,0x5F, /* 00000020 "... .B._" */ + 0x53,0x42,0x5F,0x5B,0x82,0x4A,0x18,0x50, /* 00000028 "SB_[.J.P" */ + 0x43,0x49,0x32,0x08,0x48,0x43,0x49,0x4E, /* 00000030 "CI2.HCIN" */ + 0x01,0x08,0x5F,0x48,0x49,0x44,0x0D,0x50, /* 00000038 ".._HID.P" */ + 0x4E,0x50,0x30,0x41,0x30,0x33,0x00,0x14, /* 00000040 "NP0A03.." */ + 0x18,0x5F,0x41,0x44,0x52,0x00,0xA4,0x44, /* 00000048 "._ADR..D" */ + 0x41,0x44,0x44,0x47,0x48,0x43,0x4E,0x48, /* 00000050 "ADDGHCNH" */ + 0x43,0x49,0x4E,0x0C,0x00,0x00,0x18,0x00, /* 00000058 "CIN....." */ + 0x08,0x5F,0x55,0x49,0x44,0x0A,0x03,0x14, /* 00000060 "._UID..." */ + 0x1B,0x5F,0x42,0x42,0x4E,0x00,0xA4,0x47, /* 00000068 "._BBN..G" */ + 0x42,0x55,0x53,0x47,0x48,0x43,0x4E,0x48, /* 00000070 "BUSGHCNH" */ + 0x43,0x49,0x4E,0x47,0x48,0x43,0x4C,0x48, /* 00000078 "CINGHCLH" */ + 0x43,0x49,0x4E,0x14,0x15,0x5F,0x53,0x54, /* 00000080 "CIN.._ST" */ + 0x41,0x00,0xA4,0x5C,0x2E,0x5F,0x53,0x42, /* 00000088 "A..\._SB" */ + 0x5F,0x47,0x48,0x43,0x45,0x48,0x43,0x49, /* 00000090 "_GHCEHCI" */ + 0x4E,0x14,0x48,0x05,0x5F,0x43,0x52,0x53, /* 00000098 "N.H._CRS" */ + 0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x05, /* 000000A0 "..BUF0.." */ + 0x0A,0x02,0x79,0x00,0x70,0x47,0x48,0x43, /* 000000A8 "..y.pGHC" */ + 0x4E,0x48,0x43,0x49,0x4E,0x64,0x70,0x47, /* 000000B0 "NHCINdpG" */ + 0x48,0x43,0x4C,0x48,0x43,0x49,0x4E,0x65, /* 000000B8 "HCLHCINe" */ + 0x73,0x5C,0x2E,0x5F,0x53,0x42,0x5F,0x47, /* 000000C0 "s\._SB_G" */ + 0x49,0x4F,0x52,0x64,0x65,0x42,0x55,0x46, /* 000000C8 "IORdeBUF" */ + 0x30,0x61,0x73,0x5C,0x2E,0x5F,0x53,0x42, /* 000000D0 "0as\._SB" */ + 0x5F,0x47,0x4D,0x45,0x4D,0x64,0x65,0x61, /* 000000D8 "_GMEMdea" */ + 0x62,0x73,0x5C,0x2E,0x5F,0x53,0x42,0x5F, /* 000000E0 "bs\._SB_" */ + 0x47,0x57,0x42,0x4E,0x64,0x65,0x62,0x63, /* 000000E8 "GWBNdebc" */ + 0xA4,0x63,0x5B,0x82,0x43,0x0C,0x41,0x47, /* 000000F0 ".c[.C.AG" */ + 0x50,0x42,0x08,0x5F,0x41,0x44,0x52,0x0C, /* 000000F8 "PB._ADR." */ + 0x00,0x00,0x02,0x00,0x08,0x41,0x50,0x49, /* 00000100 ".....API" */ + 0x43,0x12,0x2C,0x04,0x12,0x09,0x04,0x0B, /* 00000108 "C.,....." */ + 0xFF,0xFF,0x00,0x00,0x0A,0x10,0x12,0x09, /* 00000110 "........" */ + 0x04,0x0B,0xFF,0xFF,0x01,0x00,0x0A,0x11, /* 00000118 "........" */ + 0x12,0x0A,0x04,0x0B,0xFF,0xFF,0x0A,0x02, /* 00000120 "........" */ + 0x00,0x0A,0x12,0x12,0x0A,0x04,0x0B,0xFF, /* 00000128 "........" */ + 0xFF,0x0A,0x03,0x00,0x0A,0x13,0x08,0x50, /* 00000130 ".......P" */ + 0x49,0x43,0x4D,0x12,0x41,0x06,0x04,0x12, /* 00000138 "ICM.A..." */ + 0x16,0x04,0x0B,0xFF,0xFF,0x00,0x5C,0x2F, /* 00000140 "......\/" */ + 0x03,0x5F,0x53,0x42,0x5F,0x50,0x43,0x49, /* 00000148 "._SB_PCI" */ + 0x31,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x16, /* 00000150 "1LNKA..." */ + 0x04,0x0B,0xFF,0xFF,0x01,0x5C,0x2F,0x03, /* 00000158 ".....\/." */ + 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x31, /* 00000160 "_SB_PCI1" */ + 0x4C,0x4E,0x4B,0x42,0x00,0x12,0x17,0x04, /* 00000168 "LNKB...." */ + 0x0B,0xFF,0xFF,0x0A,0x02,0x5C,0x2F,0x03, /* 00000170 ".....\/." */ + 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x31, /* 00000178 "_SB_PCI1" */ + 0x4C,0x4E,0x4B,0x43,0x00,0x12,0x17,0x04, /* 00000180 "LNKC...." */ + 0x0B,0xFF,0xFF,0x0A,0x03,0x5C,0x2F,0x03, /* 00000188 ".....\/." */ + 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x31, /* 00000190 "_SB_PCI1" */ + 0x4C,0x4E,0x4B,0x44,0x00,0x14,0x19,0x5F, /* 00000198 "LNKD..._" */ + 0x50,0x52,0x54,0x00,0xA0,0x0B,0x92,0x50, /* 000001A0 "PRT....P" */ + 0x49,0x43,0x46,0xA4,0x50,0x49,0x43,0x4D, /* 000001A8 "ICF.PICM" */ + 0xA1,0x06,0xA4,0x41,0x50,0x49,0x43, +}; diff --git a/src/mainboard/amd/serengeti_leopard/ssdt_lb_x.dsl b/src/mainboard/amd/serengeti_leopard/ssdt_lb_x.dsl new file mode 100644 index 0000000000..712c4af235 --- /dev/null +++ b/src/mainboard/amd/serengeti_leopard/ssdt_lb_x.dsl @@ -0,0 +1,99 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// +//= + +DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440) +{ + /* + * These objects were referenced but not defined in this table + */ + External (\_SB_.PCI0, DeviceObj) + + Scope (\_SB.PCI0) + { + Name (BUSN, Package (0x04) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Name (MMIO, Package (0x10) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222 + }) + Name (PCIO, Package (0x08) + { + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee + }) + Name (SBLK, 0x11) + Name (TOM1, 0xaaaaaaaa) + Name (SBDN, 0xbbbbbbbb) + Name (HCLK, Package (0x08) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + } +} + |