summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorSubrata Banik <subratabanik@google.com>2023-01-06 16:04:09 +0530
committerSubrata Banik <subratabanik@google.com>2023-01-07 16:20:32 +0000
commit114f87bf2e697554301b5288dc1478fc851eabc3 (patch)
tree2e321a42b8a4d14f3b4001378c826e475a7c3dc2 /src/mainboard
parent19c35f1a8f71731b57e23e62be6ee1b4514a3181 (diff)
mb/google/rex: Disable stage cache
This patch disables the stage cache to save boot time. Note: S3 is not POR for Intel MTL mobile skus. Boot time is reduced by ~8ms. Boot time before: 4:end of romstage 1,391,225 (13,724) 100:start of postcar 1,403,339 (12,114) Boot time after: 4:end of romstage 1,380,262 (5,618) 100:start of postcar 1,392,323 (12,060) Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/rex/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 897bf9a7b9..a0eeaeaec0 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -21,6 +21,7 @@ config BOARD_GOOGLE_REX_COMMON
select HAVE_ACPI_TABLES
select I2C_TPM
select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_DISABLE_STAGE_CACHE
select MAINBOARD_HAS_TPM2
select PMC_IPC_ACPI_INTERFACE
select SOC_INTEL_CSE_LITE_SKU