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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-04 10:56:28 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-05 20:09:41 +0000
commit0c057c21e57e01a223d6f38c83d5e75a8e23b2ab (patch)
tree51a41024cb8f874de8618e8cc2c86a66c338d0e4 /src/mainboard
parente94a578039a698c7ffb7e2ba1ff64e9a9ea9dbf1 (diff)
soc/intel/adl, mb/google/brya: Add IPU to devicetree
BUG=b:181843816 Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/variants/baseboard/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index d82a9eb918..a0941a74f5 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -91,6 +91,7 @@ chip soc/intel/alderlake
device domain 0 on
device ref igpu on end
device ref dtt on end
+ device ref ipu on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end
device ref tbt_pcie_rp2 on end