diff options
| author | Hualin Wei <weihualin@huaqin.corp-partner.google.com> | 2024-11-01 11:37:56 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-11-06 16:47:59 +0000 |
| commit | 099bec1cc613b8fd9cd166914bbcc3d9e46d4df5 (patch) | |
| tree | a7a92794911cfc8b70f3298a4cde11955f5d9dc7 /src/mainboard | |
| parent | d88eeae6161af3d131abb90d7164c59fa620670d (diff) | |
mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:366383364
TEST=Tested on Awasuki with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/awasuki/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index cc7eba8330..e0abe19443 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" |