diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-01 15:43:36 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-24 15:28:19 +0100 |
| commit | 083b21b3545688c312f2145968597d833a00df6b (patch) | |
| tree | 35b8933f718a0d9ad71a4db37ea0fd036d828da0 /src/mainboard | |
| parent | 6ecf3f66010ec5611a83f8da77513213fe52be80 (diff) | |
rush: use padconfig API in bootblock
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on rush. Observed consistent results.
Change-Id: Ibfa6fc188a7c503cfad41420ed50c7a88fdec579
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2245478f8e21167e93a6e97b12730788a7f927ae
Original-Change-Id: I1d5d38322bda6740a0ea50b89f88b722febdee22
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210836
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rush/bootblock.c | 46 |
1 files changed, 18 insertions, 28 deletions
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c index b74baeeac7..4df915edf9 100644 --- a/src/mainboard/google/rush/bootblock.c +++ b/src/mainboard/google/rush/bootblock.c @@ -26,8 +26,6 @@ #include <soc/padconfig.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra132/clk_rst.h> -#include <soc/nvidia/tegra132/gpio.h> -#include <soc/nvidia/tegra132/pinmux.h> #include <soc/nvidia/tegra132/spi.h> /* FIXME: move back to soc code? */ #include "pmic.h" @@ -47,6 +45,22 @@ static const struct pad_config uart_console_pads[] = { PAD_CFG_UNUSED(UART2_CTS_N), }; +static const struct pad_config padcfgs[] = { + /* Board ID bits 3:0 */ + PAD_CFG_GPIO_INPUT(GPIO_X4_AUD, PINMUX_PULL_NONE), + PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE), + PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE), + PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE), + /* PMIC i2C bus */ + PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU), + PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU), + /* SPI fLash: mosi, miso, clk, cs0 */ + PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), + PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), + PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4), + PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4), +}; + void bootblock_mainboard_early_init(void) { soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads)); @@ -75,35 +89,11 @@ void bootblock_mainboard_init(void) CLK_H_I2C5 | CLK_H_APBDMA, 0, CLK_V_MSELECT, 0, 0); - // Board ID GPIOs, bits 0-3. - gpio_input(GPIO(Q3)); - gpio_input(GPIO(T1)); - gpio_input(GPIO(X1)); - gpio_input(GPIO(X4)); + /* Set up the pads required to load romstage. */ + soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); - // I2C5 (PMU) clock. - pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, - PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); - // I2C5 (PMU) data. - pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX, - PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); i2c_init(4); pmic_init(4); - /* SPI4 data out (MOSI) */ - pinmux_set_config(PINMUX_GPIO_PG6_INDEX, - PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE | - PINMUX_PULL_UP); - /* SPI4 data in (MISO) */ - pinmux_set_config(PINMUX_GPIO_PG7_INDEX, - PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE | - PINMUX_PULL_UP); - /* SPI4 clock */ - pinmux_set_config(PINMUX_GPIO_PG5_INDEX, - PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE); - /* SPI4 chip select 0 */ - pinmux_set_config(PINMUX_GPIO_PI3_INDEX, - PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); - tegra_spi_init(4); } |