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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-04-19 07:17:59 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-05-18 10:44:43 +0200 |
| commit | 08311f5033e3adccb8794b6113d72bf7a76e4d00 (patch) | |
| tree | aaf0d1ca6cacf2d5a73e45dc9f9193417a4b10fc /src/mainboard | |
| parent | 82171ea0ff9e38462e813b791dd57c8ad95dc768 (diff) | |
AGESA vendorcode: Build a common amdlib
Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.
Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/asus/m5a88-v/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 2 | ||||
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 2 |
5 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index 45c257ad24..7b6a8e6ce5 100644 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -2,8 +2,8 @@ #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c + romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c + ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c AGESA_INC := -I$(AGESA_ROOT)/ \ -I$(AGESA_ROOT)/../common \ diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index 45c257ad24..7b6a8e6ce5 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -2,8 +2,8 @@ #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c + romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c + ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c AGESA_INC := -I$(AGESA_ROOT)/ \ -I$(AGESA_ROOT)/../common \ diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index 45c257ad24..7b6a8e6ce5 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -2,8 +2,8 @@ #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c + romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c + ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c AGESA_INC := -I$(AGESA_ROOT)/ \ -I$(AGESA_ROOT)/../common \ diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 038ad8b0ec..37caa6ef45 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -16,7 +16,7 @@ #include "AGESA.h" #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <Lib/amdlib.h> +#include <amdlib.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <vendorcode/amd/cimx/sb800/SB800.h> #include <stdint.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index d0a989277e..a91bd0f2c2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -18,7 +18,7 @@ #define _PLATFORM_GNB_PCIE_COMPLEX_H #include <vendorcode/amd/agesa/f14/AGESA.h> -#include <vendorcode/amd/agesa/f14/Lib/amdlib.h> +#include <amdlib.h> /** * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) |