mb/google/nissa/var/glassway: Add GPIO table

Refer to the reference board of nivviks, and update GPIO settings
via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf.

BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: I0de743746160c6eb081cb9a061ac1703b01ba5b4
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>

2 files changed, 130 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/variants/glassway/Makefile.mk b/src/mainboard/google/brya/variants/glassway/Makefile.mk
new file mode 100644
index 0000000000..d38141ca24
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/Makefile.mk
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/glassway/gpio.c b/src/mainboard/google/brya/variants/glassway/gpio.c
new file mode 100644
index 0000000000..d3510a17c5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/gpio.c
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage for glassway */
+static const struct pad_config override_gpio_table[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A20  : DDSP_HPD2 ==> NC */
+	PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D6  : WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D15 : ISH_UART0_RTS# ==> NC */
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
+	/* D16 : ISH_UART0_CTS# ==> NC */
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+	/* D17 : PCIE SLOT1 WAKE N */
+	PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* E4 : SDD_STRAP1 */
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	/* E5 : SDD_STRAP2 */
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
+	/* E21 : DDP2_CTRLDATA ==> NC */
+	PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
+	/* F12 : WWAN_RST_L */
+	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+	/* F13 : GSXSLOAD ==> NC */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H22 : IMGCLKOUT3 ==> NC */
+	PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+	/* R4 : I2S2_SCLK ==> DMIC_UCAM_CLK_R */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : I2S2_SFRM ==> DMIC_UCAM_DATA_R */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : DMIC_CLK_A_1A ==> NC */
+	PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
+
+	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
+	/* BT_I2S_BCLK */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
+	/* BT_I2S_SYNC */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
+	/* BT_I2S_SDO */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
+	/* BT_I2S_SDI */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
+	/* SSP2_SCLK */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* SSP2_SFRM */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* SSP_TXD */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* SSP_RXD */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock for glassway */
+static const struct pad_config early_gpio_table[] = {
+	/* F12 : GSXDOUT ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
+	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* Enable touchscreen, hold in reset */
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* H12 : UART0_RTS# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H12, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}