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authorMike Loptien <mike.loptien@se-eng.com>2013-03-15 13:17:52 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-17 19:54:40 +0100
commit00a0e76bc5ffaba01c98f1c1384b0499516fdaef (patch)
tree94337417d09c4a8f71f9f75703a3c7f353ede12c /src/mainboard
parent9c3d112bb686f1c044aeb501ef810e2fb8c9310e (diff)
AMD Fam14 DSDT: Add OSC method
The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. This is the same change made to Persimmon with Change-ID I149428: http://review.coreboot.org/#/c/2684/ Change-Id: If6dd1a558d9c319d9a41ce63588550c8e81e595f Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/inagua/dsdt.asl14
-rw-r--r--src/mainboard/amd/south_station/dsdt.asl14
-rw-r--r--src/mainboard/amd/union_station/dsdt.asl14
3 files changed, 39 insertions, 3 deletions
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
index 148d7b074b..dff59170de 100644
--- a/src/mainboard/amd/inagua/dsdt.asl
+++ b/src/mainboard/amd/inagua/dsdt.asl
@@ -1157,8 +1157,20 @@ DefinitionBlock (
Device(PCI0) {
External (TOM1)
External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
+ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+
+ /* Operating System Capabilities Method */
+ Method(_OSC,4)
+ { /* Check for proper PCI/PCIe UUID */
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+ }
+
Method(_BBN, 0) { /* Bus number = 0 */
Return(0)
}
diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl
index 148d7b074b..dff59170de 100644
--- a/src/mainboard/amd/south_station/dsdt.asl
+++ b/src/mainboard/amd/south_station/dsdt.asl
@@ -1157,8 +1157,20 @@ DefinitionBlock (
Device(PCI0) {
External (TOM1)
External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
+ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+
+ /* Operating System Capabilities Method */
+ Method(_OSC,4)
+ { /* Check for proper PCI/PCIe UUID */
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+ }
+
Method(_BBN, 0) { /* Bus number = 0 */
Return(0)
}
diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl
index 1d2435c0b6..b59ea7b39b 100644
--- a/src/mainboard/amd/union_station/dsdt.asl
+++ b/src/mainboard/amd/union_station/dsdt.asl
@@ -1157,8 +1157,20 @@ DefinitionBlock (
Device(PCI0) {
External (TOM1)
External (TOM2)
- Name(_HID, EISAID("PNP0A03"))
+ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+
+ /* Operating System Capabilities Method */
+ Method(_OSC,4)
+ { /* Check for proper PCI/PCIe UUID */
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+ }
+
Method(_BBN, 0) { /* Bus number = 0 */
Return(0)
}