diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-01-07 12:09:55 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-01-08 19:13:13 +0000 |
| commit | e55e61f88929cc51950817c5769993c7a7e5d9df (patch) | |
| tree | 853d7816d5a3518d92b6695d4635c9aaeaa76d29 /src/mainboard | |
| parent | cae7944fc310be9ef6b0c105d5a6a3e9b113e507 (diff) | |
mb/google/sarien: Set minimum assertion width values
Explicitly configure the minimum assertion width values to ensure
that they are set as expected and are not using unknown defaults.
Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 5fdf8fd771..cccddce712 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -23,6 +23,10 @@ chip soc/intel/cannonlake register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s register "speed_shift_enable" = "1" register "s0ix_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 358d131b3f..b590bac4bf 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -27,6 +27,10 @@ chip soc/intel/cannonlake register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s register "speed_shift_enable" = "1" register "s0ix_enable" = "1" |