mb/ocp/monolake: add TPM and IPMI support

Changes includes:

- enable TPM1 + add entry in devicetree
- configure LPC IO to make IPMI work + add entry in devicetree
- introduce DSDT and SMBIOS entries for IPMI to make it detectable
  by ipmi_si driver

Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

5 files changed, 148 insertions, 3 deletions

diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig
index aff6619b87..037c322620 100644
--- a/src/mainboard/ocp/monolake/Kconfig
+++ b/src/mainboard/ocp/monolake/Kconfig
@@ -11,6 +11,11 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_USES_IFD_GBE_REGION
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM1
+
+config INTEGRATED_UART
+	def_bool n
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb
index 30d99c22eb..2d91b73b02 100644
--- a/src/mainboard/ocp/monolake/devicetree.cb
+++ b/src/mainboard/ocp/monolake/devicetree.cb
@@ -7,7 +7,14 @@ chip soc/intel/fsp_broadwell_de
 		device pci 14.0 on end # xHCI Controller
 		device pci 19.0 on end # Gigabit LAN Controller
 		device pci 1d.0 on end # EHCI Controller
-		device pci 1f.0 on end # LPC Bridge
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+			chip drivers/generic/generic		# BMC KCS
+				device pnp ca2.0 on end
+			end
+		end # LPC Bridge
 		device pci 1f.2 on end # SATA Controller
 		device pci 1f.3 on end # SMBus Controller
 		device pci 1f.5 on end # SATA Controller
diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl
index 1248703266..72b1c3c086 100644
--- a/src/mainboard/ocp/monolake/dsdt.asl
+++ b/src/mainboard/ocp/monolake/dsdt.asl
@@ -27,6 +27,9 @@ DefinitionBlock(
 {
 	#include "acpi/platform.asl"
 
+	Name (IDTP, 0x0CA2)
+	Name (ICDP, 0x0CA6)
+
 	Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
 	Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
 
@@ -290,5 +293,97 @@ DefinitionBlock(
 		}
 	}
 
+	Scope (_SB.PCI0.LPC0)
+	{
+		Device (SPMI)
+		{
+			Name (_HID, EisaId ("IPI0001"))
+			Name (_STR, Unicode ("IPMI_KCS"))
+			Name (_UID, 0x00)
+			OperationRegion (IPST, SystemIO, ICDP, 0x01)
+			Field (IPST, ByteAcc, NoLock, Preserve)
+			{
+				STAS,		8
+			}
+			Method (_STA, 0, NotSerialized) {
+				Return (0x0f)
+			}
+			Name (ICRS, ResourceTemplate ()
+			{
+				IO (Decode16,
+					0x0000,
+					0x0000,
+					0x00,
+					0x00,
+					_Y01)
+				IO (Decode16,
+					0x0000,
+					0x0000,
+					0x00,
+					0x00,
+					_Y02)
+
+			})
+			Method (_CRS, 0, NotSerialized)
+			{
+				CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB)
+				CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH)
+				CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL)
+				CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB)
+				CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH)
+				CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL)
+
+				IPDB = IDTP
+				IPDH = IDTP
+				IPDL = 0x01
+
+				IPCB = ICDP
+				IPCH = ICDP
+				IPCL = 0x01
+
+				Return (ICRS)
+			}
+			Method (_IFT, 0, NotSerialized) {
+				Return (0x01)
+			}
+			Method(_SRV, 0, NotSerialized) {
+				Return (0x0200)
+			}
+		}
+
+		Device (SYSR)
+		{
+			Name (_HID, EisaId ("PNP0C02"))
+
+			Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+			{
+				IO (Decode16,
+					0x0CA2,
+					0x0CA2,
+					0x01,
+					0x01,
+				)
+				IO (Decode16,
+					0x0CA6,
+					0x0CA6,
+					0x01,
+					0x01,
+				)
+				IO (Decode16,
+					0x0CA8,
+					0x0CA8,
+					0x01,
+					0x01,
+				)
+				IO (Decode16,
+					0x0CAC,
+					0x0CAC,
+					0x01,
+					0x01,
+				)
+			})
+		}
+	}
+
 	#include "acpi/mainboard.asl"
 }
diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c
index 93c2a58f74..d457859d44 100644
--- a/src/mainboard/ocp/monolake/mainboard.c
+++ b/src/mainboard/ocp/monolake/mainboard.c
@@ -15,17 +15,51 @@
  */
 
 #include <device/device.h>
+#include <smbios.h>
 #if CONFIG(VGA_ROM_RUN)
 #include <x86emu/x86emu.h>
 #endif
 
+#define BMC_KCS_BASE 0xca2
+#define INTERFACE_IS_IO 0x1
+
+#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+static int mainboard_smbios_data(struct device *dev, int *handle,
+				 unsigned long *current)
+{
+	int len = 0;
+
+	// add IPMI Device Information
+	len += smbios_write_type38(
+		current, handle,
+		SMBIOS_BMC_INTERFACE_KCS,
+		0x20,				// IPMI Version
+		0x20,				// I2C address
+		0xff,				// no NV storage
+		BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address
+		0x40,
+		0); // no IRQ
+
+	return len;
+}
+#endif
+
 /*
  * mainboard_enable is executed as first thing after enumerate_buses().
  * This is the earliest point to add customization.
  */
 static void mainboard_enable(struct device *dev)
 {
+#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+	dev->ops->get_smbios_data = mainboard_smbios_data;
+#endif
 
+	/* Enable access to the BMC IPMI via KCS */
+	struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0);
+	struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE);
+	res->base = BMC_KCS_BASE;
+	res->size = 1;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index 2bb50f097b..f3ec7e32b8 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -20,6 +20,9 @@
 #include <cpu/x86/msr.h>
 #include <cf9_reset.h>
 #include <console/console.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
 
 /**
  * /brief mainboard call for setup that needs to be done before fsp init
@@ -49,7 +52,9 @@ void early_mainboard_romstage_entry(void)
  */
 void late_mainboard_romstage_entry(void)
 {
-
+	// IPMI through BIC
+	pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
+			   0x0c0ca1);
 }
 
 /**
@@ -57,5 +62,4 @@ void late_mainboard_romstage_entry(void)
  */
 void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 {
-
 }