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authorMichael Niewöhner <foss@mniewoehner.de>2020-09-24 10:17:58 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-25 00:29:53 +0000
commit92c1546c01795f8c8c079e7ea03c9cb36314e92a (patch)
treef13b97ba4cba74cde3e3e482efb78684f6ebba53 /src/mainboard
parent44df56edcededb72d12289a6be8b7e2fb8fc1da0 (diff)
mb/clevo/cml-u: remove the duplicate WiFi PCIe device in devicetree
Change-Id: Ibb46bbf0c889bb8b3fd1a4c0331dc719baffc7a2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45678 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index b1899417b9..55c5c6ebf8 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -142,15 +142,14 @@ chip soc/intel/cannonlake
end
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8
- device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
+ chip drivers/intel/wifi
+ device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
+ end
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieRpSlotImplemented[7]" = "1"
- chip drivers/intel/wifi
- device pci 00.0 on end
- end
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
device pci 1d.0 on # PCI Express Port 9