summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorVenkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>2016-09-08 15:25:35 -0700
committerMartin Roth <martinroth@google.com>2016-09-12 19:49:08 +0200
commit6584973bdc2ae57311f4a20041975bfac34d0d59 (patch)
tree76c9e86119a4e7fe30e02ed9748e2eb2e5fcb8ad /src/mainboard
parent91aea428b5932c031b81a6c4921ac416f2b2c995 (diff)
mainboard/google/reef: Disable CLKREQ of unused PCIe root ports
1. Removes PCIe blocker for S0ix. 2. Set the correct PCIe root port for wifi/bt on EVT. 3. Turn off CLKREQs of unused PCIe root ports to power gate the IP. Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/reef/variants/baseboard/devicetree.cb9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 2ac20de2dc..e663787ae2 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -4,7 +4,14 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ # Disable unused clkreq of PCIe root ports
+ register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.