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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-06-09 18:57:23 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-11 02:01:47 +0100
commit2b206775fa5e956772b54295a563c5a69e2117b6 (patch)
tree37fbd7671076efec31d3c09b0fca16e9c8575af9 /src/mainboard
parent5d7dc5545dc51152abada7677073ab1e8ee97960 (diff)
mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs
Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11982 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asus/kgpe-d16/mainboard.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c
index 802b8559ed..d71df9e38f 100644
--- a/src/mainboard/asus/kgpe-d16/mainboard.c
+++ b/src/mainboard/asus/kgpe-d16/mainboard.c
@@ -72,6 +72,29 @@ static void mainboard_enable(device_t dev)
/* get_ide_dma66(); */
}
+/* override the default SATA PHY setup */
+void sb7xx_51xx_setup_sata_phys(struct device *dev)
+{
+ /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+ pci_write_config16(dev, 0x86, 0x2c00);
+
+ /* RPR7.6.2 SATA GENI PHY ports setting */
+ pci_write_config32(dev, 0x88, 0x01b48016);
+ pci_write_config32(dev, 0x8c, 0x01b48016);
+ pci_write_config32(dev, 0x90, 0x01b48016);
+ pci_write_config32(dev, 0x94, 0x01b48016);
+ pci_write_config32(dev, 0x98, 0x01b48016);
+ pci_write_config32(dev, 0x9c, 0x01b48016);
+
+ /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+ pci_write_config16(dev, 0xa0, 0xa07a);
+ pci_write_config16(dev, 0xa2, 0xa07a);
+ pci_write_config16(dev, 0xa4, 0xa07a);
+ pci_write_config16(dev, 0xa6, 0xa07a);
+ pci_write_config16(dev, 0xa8, 0xa07a);
+ pci_write_config16(dev, 0xaa, 0xa07a);
+}
+
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};