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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-03-06 10:51:30 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-10 09:56:36 +0000
commit01ec713c269f68e5a2918cfb8ee14d6d1f40eda8 (patch)
tree71a68bb812431b5ade63789d28866691b371004f /src/mainboard
parentf6f54dd3fa4f30d2078b76d0adcceb2a14cde3c5 (diff)
mb/google/volteer: set TcssXhciEn to 1
BUG=144874778 TEST=Built with Volteer recipe and verified USB functionality Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 070e4f6786..dd6895b131 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -110,6 +110,9 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # TCSS USB3
+ register "TcssXhciEn" = "1"
+
# DP port
register "DdiPortAConfig" = "1" # eDP
register "DdiPortBConfig" = "0"