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authorDavid Hendricks <dhendrix@chromium.org>2013-02-05 14:43:52 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-06 00:41:15 +0100
commit00e480e22d00088d4d6f8bb6b0a6b5c1f840f6a2 (patch)
treea532c97c0fcacffe59b09c24067eff57090753eb /src/mainboard
parent6aaf856cd2f47d762962a8c06d73f3bb2e61e146 (diff)
snow: use bootblock build class for GPIO
This gets rid of a bunch of copy + pasted GPIO code. Change-Id: I548b2b5d63642a9da185eb7b34f80cbebf9b124f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/snow/bootblock.c82
1 files changed, 0 insertions, 82 deletions
diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c
index 2855ddbc27..0507fb2bda 100644
--- a/src/mainboard/google/snow/bootblock.c
+++ b/src/mainboard/google/snow/bootblock.c
@@ -42,88 +42,6 @@
#define EXYNOS5_CLOCK_BASE 0x10010000
-struct gpio_info {
- unsigned int reg_addr; /* Address of register for this part */
- unsigned int max_gpio; /* Maximum GPIO in this part */
-};
-
-static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = {
- { EXYNOS5_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 },
- { EXYNOS5_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 },
- { EXYNOS5_GPIO_PART3_BASE, GPIO_MAX_PORT_PART_3 },
- { EXYNOS5_GPIO_PART4_BASE, GPIO_MAX_PORT_PART_4 },
- { EXYNOS5_GPIO_PART5_BASE, GPIO_MAX_PORT_PART_5 },
- { EXYNOS5_GPIO_PART6_BASE, GPIO_MAX_PORT },
-};
-
-static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio)
-{
- const struct gpio_info *data;
- unsigned int upto;
- int i;
-
- for (i = upto = 0, data = gpio_data; i < EXYNOS_GPIO_NUM_PARTS;
- i++, upto = data->max_gpio, data++) {
- if (gpio < data->max_gpio) {
- struct s5p_gpio_bank *bank;
-
- bank = (struct s5p_gpio_bank *)data->reg_addr;
- bank += (gpio - upto) / GPIO_PER_BANK;
- return bank;
- }
- }
-
-#ifndef CONFIG_SPL_BUILD
- assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */
-#endif
- return NULL;
-}
-
-#define CON_MASK(x) (0xf << ((x) << 2))
-#define CON_SFR(x, v) ((v) << ((x) << 2))
-
-/* This macro gets gpio pin offset from 0..7 */
-#define GPIO_BIT(x) ((x) & 0x7)
-
-void gpio_cfg_pin(int gpio, int cfg)
-{
- unsigned int value;
- struct s5p_gpio_bank *bank = gpio_get_bank(gpio);
-
- value = readl(&bank->con);
- value &= ~CON_MASK(GPIO_BIT(gpio));
- value |= CON_SFR(GPIO_BIT(gpio), cfg);
- writel(value, &bank->con);
-}
-
-/* Pull mode */
-#define EXYNOS_GPIO_PULL_NONE 0x0
-#define EXYNOS_GPIO_PULL_DOWN 0x1
-#define EXYNOS_GPIO_PULL_UP 0x3
-
-#define PULL_MASK(x) (0x3 << ((x) << 1))
-#define PULL_MODE(x, v) ((v) << ((x) << 1))
-
-void gpio_set_pull(int gpio, int mode)
-{
- unsigned int value;
- struct s5p_gpio_bank *bank = gpio_get_bank(gpio);
-
- value = readl(&bank->pull);
- value &= ~PULL_MASK(GPIO_BIT(gpio));
-
- switch (mode) {
- case EXYNOS_GPIO_PULL_DOWN:
- case EXYNOS_GPIO_PULL_UP:
- value |= PULL_MODE(GPIO_BIT(gpio), mode);
- break;
- default:
- break;
- }
-
- writel(value, &bank->pull);
-}
-
#define CONFIG_SYS_CLK_FREQ 24000000
void puts(const char *s);