summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorGerd Hoffmann <kraxel@redhat.com>2013-08-09 10:02:22 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2013-08-15 20:37:48 +0200
commita4e70578db9268c4f9847ba43e754f3e95d7a4e5 (patch)
tree014036bfc34d28bb949d8266dbb5b7f03671b7e6 /src/mainboard
parent1e1a1798faf9715ceb2bd34b619c3c21f03ce89a (diff)
qemu: fix ioapic reservation
The slightly hackish ioapic ressource reservation is needed for i440fx emulation only, for q35 the ich9 southbridge driver handles this just fine. [ Side note: The i440fx chipset emulated by qemu is pimped up with alot of stuff which never existed on real hardware, which leads to tweaks like this one. ] Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/emulation/qemu-i440fx/northbridge.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index f975b6cdc4..c08d59e795 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -52,6 +52,9 @@ static void cpu_pci_domain_set_resources(device_t dev)
static void cpu_pci_domain_read_resources(struct device *dev)
{
+ u16 nbid = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
+ int i440fx = (nbid == 0x1237);
+// int q35 = (nbid == 0x29c0);
struct resource *res;
unsigned long tomk = 0, high;
int idx = 10;
@@ -89,14 +92,17 @@ static void cpu_pci_domain_read_resources(struct device *dev)
high_tables_size = HIGH_MEMORY_SIZE;
#endif
- /* Reserve space for the IOAPIC. This should be in the Southbridge,
- * but I couldn't tell which device to put it in. */
- res = new_resource(dev, 2);
- res->base = IO_APIC_ADDR;
- res->size = 0x100000UL;
- res->limit = 0xffffffffUL;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_ASSIGNED;
+ if (i440fx) {
+ /* Reserve space for the IOAPIC. This should be in
+ * the Southbridge, but I couldn't tell which device
+ * to put it in. */
+ res = new_resource(dev, 2);
+ res->base = IO_APIC_ADDR;
+ res->size = 0x100000UL;
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ }
/* Reserve space for the LAPIC. There's one in every processor, but
* the space only needs to be reserved once, so we do it here. */