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authorBora Guvendik <bora.guvendik@intel.com>2019-10-09 14:18:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-10-16 14:13:07 +0000
commit73ffd6acdf468f7d15a4927d30883e45f4706d6f (patch)
treeea0fc7454fb10d8c0b3a36af4eb51ab995b8e9e3 /src/mainboard
parent469af0348e2e61112ee98007d41aaaa43135a776 (diff)
mb/google/drallion: Add new SPD file for drallion
Add the SPD data for MT40A1G16KD-062E:E BUG=b:139397313 TEST=Compile successfully. Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex32
-rw-r--r--src/mainboard/google/drallion/variants/drallion/Makefile.inc1
-rw-r--r--src/mainboard/google/drallion/variants/drallion/memory.c2
3 files changed, 34 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex
new file mode 100644
index 0000000000..4fe4d0e657
--- /dev/null
+++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36
+0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 34 41 54 46 35 31 32
+36 34 48 5A 2D 33 47 32 45 31 20 20 20 31 80 2C
+45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc
index ef3d54d185..ccbcb08da8 100644
--- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc
+++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc
@@ -22,6 +22,7 @@ SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b10001
SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001
SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011
SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011
+SPD_SOURCES += micron_dimm_MT40A1G16KD-062EE # 0b11010
bootblock-y += gpio.c
ramstage-y += gpio.c
diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c
index 37d009adf9..9c4135dfdc 100644
--- a/src/mainboard/google/drallion/variants/drallion/memory.c
+++ b/src/mainboard/google/drallion/variants/drallion/memory.c
@@ -24,7 +24,7 @@ static const int spd_index[32] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 4, 3, 6, 1, 0, 0, 0,
- 0, 5, 0, 7, 2, 0, 0, 0
+ 0, 5, 8, 7, 2, 0, 0, 0
};
const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)