- First pass at getting the powerpc ports to compile

  The static device tree is not built properly at all yet, but at least we get through it.
  FIXME (What is the proper way to handle add in boards?)
- Add generic div64 support and ppc div64 support
- Fix abuild so it properly generates the CC line when cross compiling.
- Add one more possible ppc cross compiler target


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 297 insertions, 16 deletions

diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb
index 4b76162e17..9f071bf621 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Config.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb
@@ -9,12 +9,12 @@ initobject init.c
 driver pci_bridge.c
 
 arch ppc end
-cpu ppc/ppc4xx end
+chip cpu/ppc/ppc4xx device pnp 0.0 on end end
 
 ##
 ## Include the secondary Configuration files 
 ##
-southbridge winbond/w83c553 end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
 
 ##
 ## Build the objects we have code for in this directory.
diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb
index 9acea4955f..d37db77dc2 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Options.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb
@@ -8,6 +8,41 @@ uses ISA_IO_BASE
 uses ISA_MEM_BASE 
 uses TTYS0_BASE 
 uses _IO_BASE 
+
+uses CPU_OPT
+uses CROSS_COMPILE 
+uses HAVE_OPTION_TABLE
+uses CONFIG_COMPRESS 
+uses CONFIG_CHIP_CONFIGURE
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_USE_INIT
+uses CONFIG_CONSOLE_SERIAL8250 
+uses TTYS0_BAUD TTYS0_DIV
+uses NO_POST
+uses CONFIG_IDE
+uses CONFIG_FS_STREAM
+uses CONFIG_FS_EXT2
+uses CONFIG_FS_ISO9660
+uses CONFIG_FS_FAT
+uses AUTOBOOT_CMDLINE
+uses CONFIG_SYS_CLK_FREQ
+uses IDE_BOOT_DRIVE
+#uses IDE_SWAB
+uses IDE_OFFSET 
+uses ROM_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+#uses _RAMSTART
+uses EMBEDDED_RAM_SIZE
+uses STACK_SIZE HEAP_SIZE
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -33,3 +68,74 @@ default _IO_BASE=ISA_IO_BASE
 ##
 default TTYS0_BASE=0xef600300-ISA_IO_BASE
 
+## Enable PPC405 instructions
+default CPU_OPT="-Wa,-m405"
+default CPU_OPT=""
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## Use chip configuration
+default CONFIG_CHIP_CONFIGURE=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+# Divisor of 69 == 9600 baud due to weird clocking
+default TTYS0_DIV=69
+default TTYS0_BAUD=9600
+
+## Boot linux from IDE
+default CONFIG_IDE=1
+default CONFIG_FS_STREAM=1
+default CONFIG_FS_EXT2=1
+default CONFIG_FS_ISO9660=1
+default CONFIG_FS_FAT=1
+default AUTOBOOT_CMDLINE="hda1:/vmlinuz"
+
+default ROM_SIZE=1048576
+
+## Board has fixed size RAM
+default EMBEDDED_RAM_SIZE=64*1024*1024
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+
+##
+## Use a 64K stack
+##
+default STACK_SIZE=0x10000
+
+##
+## Use a 64K heap
+##
+default HEAP_SIZE=0x10000
+
+##
+## System clock
+##
+default CONFIG_SYS_CLK_FREQ=33
+
+##
+default _ROMBASE=0xfff00000
+
+## Reset vector address
+default _RESET=0xfffffffc
+
+## Exception vectors
+default _EXCEPTION_VECTORS=_ROMBASE+0x100
+
+## linuxBIOS ROM start address
+default _ROMSTART=0xfff03000
+
+## linuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+
+### End Options.lb
+end
diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb
index f33ce4bede..94e0ba79f1 100644
--- a/src/mainboard/motorola/sandpoint/Config.lb
+++ b/src/mainboard/motorola/sandpoint/Config.lb
@@ -20,30 +20,30 @@ object clock.o
 arch ppc end
 
 if CONFIG_SANDPOINT_ALTIMUS
-	pmc altimus/mpc7410 end
-#	pmc altimus/mpc7400 end
-#	pmc altimus/mpc75x end
+	chip pmc/altimus/mpc7410 device pnp 0.0 on end end
+#	chip pmc/altimus/mpc7400 device pnp 0.0 on end end
+#	chip pmc/altimus/mpc75x device pnp 0.0 on end end
 end
 if CONFIG_SANDPOINT_TALUS
-	pmc talus/mpc74x end
-	pmc talus/mpc603 end
+	chip pmc/talus/mpc74x device pnp 0.0 on end end
+	chip pmc/talus/mpc603 device pnp 0.0 on end end
 end
 if CONFIG_SANDPOINT_UNITY
-	pmc unity/mpc824x end
+	chip pmc/unity/mpc824x device pnp 0.0 on end end
 end
 if CONFIG_SANDPOINT_VALIS
-	pmc valis/mpc745x end
+	chip pmc/valis/mpc745x device pnp 0.0 on end end
 end
 if CONFIG_SANDPOINT_GYRUS
-	pmc gyrus/mpc744x end
+	chip pmc/gyrus/mpc744x device pnp 0.0 on end end
 end
 
 ##
 ## Include the secondary Configuration files 
 ##
-southbridge winbond/w83c553 end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
 
-superio NSC/pc97307 end
+chip superio/NSC/pc97307 device pnp 0.0 on end end
 
 ##
 ## Build the objects we have code for in this directory.
diff --git a/src/mainboard/motorola/sandpoint/Options.lb b/src/mainboard/motorola/sandpoint/Options.lb
index 5ca5007883..f17fc0ef82 100644
--- a/src/mainboard/motorola/sandpoint/Options.lb
+++ b/src/mainboard/motorola/sandpoint/Options.lb
@@ -10,6 +10,39 @@ uses PCIC0_CFGDATA
 uses PNP_CFGADDR
 uses PNP_CFGDATA
 uses _IO_BASE
+
+uses CROSS_COMPILE 
+uses HAVE_OPTION_TABLE
+uses CONFIG_SANDPOINT_ALTIMUS 
+uses CONFIG_COMPRESS 
+uses DEFAULT_CONSOLE_LOGLEVEL 
+uses CONFIG_USE_INIT
+uses CONFIG_CHIP_CONFIGURE
+uses NO_POST
+uses CONFIG_CONSOLE_SERIAL8250 
+uses TTYS0_BASE 
+uses CONFIG_IDE
+uses CONFIG_FS_STREAM 
+uses CONFIG_FS_EXT2
+uses CONFIG_FS_ISO9660
+uses CONFIG_FS_FAT
+uses AUTOBOOT_CMDLINE
+uses PAYLOAD_SIZE
+uses ROM_SIZE
+uses ROM_IMAGE_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+uses _RAMSTART
+uses STACK_SIZE
+uses HEAP_SIZE
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -25,3 +58,65 @@ default PCIC0_CFGDATA=0xfee00000
 default PNP_CFGADDR=0x15c
 default PNP_CFGDATA=0x15d
 default _IO_BASE=ISA_IO_BASE
+
+
+## use a cross compiler
+#default CROSS_COMPILE="powerpc-eabi-"
+#default CROSS_COMPILE="ppc_74xx-"
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## Use static configuration
+default CONFIG_CHIP_CONFIGURE=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+default TTYS0_BASE=0x3f8
+
+## Load payload using filo
+default CONFIG_IDE=1
+default CONFIG_FS_STREAM=1
+default CONFIG_FS_EXT2=1
+default CONFIG_FS_ISO9660=1
+default CONFIG_FS_FAT=1
+default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
+
+# LinuxBIOS must fit into 128KB
+default ROM_IMAGE_SIZE=131072
+default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
+default PAYLOAD_SIZE=262144
+
+# Set stack and heap sizes (stage 2)
+default STACK_SIZE=0x10000
+default HEAP_SIZE=0x10000
+
+# Sandpoint Demo Board
+## Base of ROM
+default _ROMBASE=0xfff00000
+
+## Sandpoint reset vector
+default _RESET=_ROMBASE+0x100
+
+## Exception vectors (other than reset vector)
+default _EXCEPTION_VECTORS=_RESET+0x100
+
+## Start of linuxBIOS in the boot rom
+## = _RESET + exeception vector table size
+default _ROMSTART=_RESET+0x3100
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+default _RAMSTART=0x00100000
+
+default CONFIG_SANDPOINT_ALTIMUS=1
+
+### End Options.lb
+end
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index 943018d025..775aad36f8 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -16,17 +16,17 @@ object clock.o
 arch ppc end
 
 if CONFIG_BRIQ_750FX
-	cpu ppc/ppc7xx end
+	chip cpu/ppc/ppc7xx device pnp 0.0 on end end
 end
 if CONFIG_BRIQ_7400
-	cpu ppc/mpc74xx end
+	chip cpu/ppc/mpc74xx device pnp 0.0 on end  end
 end
 
 ##
 ## Include the secondary Configuration files 
 ##
-northbridge ibm/cpc710 end
-southbridge winbond/w83c553 end
+chip northbridge/ibm/cpc710 device pnp 0.0 on end end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
 
 ##
 ## Build the objects we have code for in this directory.
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb
index 37bfa24c72..557290f8ff 100644
--- a/src/mainboard/totalimpact/briq/Options.lb
+++ b/src/mainboard/totalimpact/briq/Options.lb
@@ -11,6 +11,32 @@ uses ISA_MEM_BASE
 uses PCIC0_CFGADDR
 uses PCIC0_CFGDATA
 uses _IO_BASE
+uses CROSS_COMPILE 
+uses HAVE_OPTION_TABLE
+uses CONFIG_COMPRESS 
+uses DEFAULT_CONSOLE_LOGLEVEL 
+uses CONFIG_USE_INIT
+uses NO_POST
+uses CONFIG_CONSOLE_SERIAL8250 
+uses CONFIG_IDE_STREAM 
+uses IDE_BOOT_DRIVE
+uses IDE_SWAB IDE_OFFSET 
+uses ROM_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+uses _RAMSTART
+uses STACK_SIZE
+uses HEAP_SIZE
+uses CONFIG_BRIQ_750FX 
+uses CONFIG_BRIQ_7400
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -33,3 +59,57 @@ default TTYS0_DIV=4
 ## Set UART base address
 ##
 default TTYS0_BASE=0x3f8
+
+## use a cross compiler
+#default CROSS_COMPILE="powerpc-eabi-"
+#default CROSS_COMPILE="ppc_74xx-"
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Boot linux from IDE
+default CONFIG_IDE_STREAM=1
+default IDE_BOOT_DRIVE=0
+default IDE_SWAB=1
+default IDE_OFFSET=0
+
+# ROM is 1Mb
+default ROM_SIZE=1048576
+
+# Set stack and heap sizes (stage 2)
+default STACK_SIZE=0x10000
+default HEAP_SIZE=0x10000
+
+# Sandpoint Demo Board
+## Base of ROM
+default _ROMBASE=0xfff00000
+
+## Sandpoint reset vector
+default _RESET=_ROMBASE+0x100
+
+## Exception vectors (other than reset vector)
+default _EXCEPTION_VECTORS=_RESET+0x100
+
+## Start of linuxBIOS in the boot rom
+## = _RESET + exeception vector table size
+default _ROMSTART=_RESET+0x3100
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+default _RAMSTART=0x00100000
+
+default CONFIG_BRIQ_750FX=1
+#default CONFIG_BRIQ_7400=1
+
+### End Options.lb
+end