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authorDuncan Laurie <dlaurie@chromium.org>2015-08-28 17:22:04 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-08 11:31:27 +0000
commit5c44d2e23ec90eac5996aebbae214d3fe84b53ce (patch)
tree74f0d0b528a3b30fe232e775d2b5ef12802b3264 /src/mainboard
parent3745c65c832ab0abb557cf68e92a6ad2c09f0faf (diff)
glados: Disable unused USB ports
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados, ensure expected USB ports still work Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163 Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296035 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11548 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/glados/devicetree.cb12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 9bb065de17..2c6d99736f 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -20,6 +20,18 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
+ register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */
+ register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */
+ register "PortUsb20Enable[2]" = "1" /* Bluetooth */
+ register "PortUsb20Enable[4]" = "1" /* Type-A Port 1 */
+ register "PortUsb20Enable[6]" = "1" /* Camera */
+ register "PortUsb20Enable[8]" = "1" /* Type-A Port 2 */
+
+ register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */
+ register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */
+ register "PortUsb30Enable[2]" = "1" /* Type-A Port 1 */
+ register "PortUsb30Enable[3]" = "1" /* Type-A Port 2 */
+
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"