soc/intel/alderlake: Refactor PCIE port config

Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

2 files changed, 75 insertions, 67 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 51a39c0f7a..647ea42ffe 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -14,42 +14,13 @@ chip soc/intel/alderlake
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
 
-	# Enable WLAN PCIE 5 using clk 2
-	register "PchPcieRpEnable[5]" = "1"
-	register "PcieRpLtrEnable[5]" = "1"
-	register "PcieClkSrcUsage[2]" = "5"
-	register "PcieClkSrcClkReq[2]" = "2"
-	register "PcieRpAdvancedErrorReporting[5]" = "1"
-
-	# Enable WWAN PCIE 6 using clk 5
-	register "PchPcieRpEnable[6]" = "1"
-	register "PcieRpLtrEnable[6]" = "1"
-	register "PcieClkSrcUsage[5]" = "6"
-	register "PcieClkSrcClkReq[5]" = "5"
-	register "PcieRpAdvancedErrorReporting[6]" = "1"
-
-	# Enable SD Card PCIE 8 using clk 3
-	register "PchPcieRpEnable[7]" = "1"
-	register "PcieRpLtrEnable[7]" = "1"
-	register "PcieRpHotPlug[7]" = "1"
-	register "PcieClkSrcUsage[3]" = "7"
-	register "PcieClkSrcClkReq[3]" = "3"
-	register "PcieRpAdvancedErrorReporting[7]" = "1"
-
-	# Enable NVMe PCIE 9 using clk 1
-	register "PchPcieRpEnable[8]" = "1"
-	register "PcieRpLtrEnable[8]" = "1"
-	register "PcieClkSrcUsage[1]" = "8"
-	register "PcieClkSrcClkReq[1]" = "1"
-	register "PcieRpAdvancedErrorReporting[8]" = "1"
-
 	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
 	register "SerialIoGSpiMode" = "{
@@ -121,10 +92,38 @@ chip soc/intel/alderlake
 		end
 		device ref heci1 on end
 		device ref sata on end
-		device ref pcie_rp5 on end	#PCIE5 WLAN
-		device ref pcie_rp6 on end	#PCIE6 WWAN
-		device ref pcie_rp8 on end	#PCIE8 SD card
-		device ref pcie_rp9 on end	#PCIE9-12 SSD
+		device ref pcie_rp5 on
+			# Enable WLAN PCIE 5 using clk 2
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE5 WLAN
+		device ref pcie_rp6 on
+			# Enable WWAN PCIE 6 using clk 5
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE6 WWAN
+		device ref pcie_rp8 on
+			# Enable SD Card PCIE 8 using clk 3
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			# Enable NVMe PCIE 9 using clk 1
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	#PCIE9-12 SSD
 		device ref uart0 on end
 		device ref gspi1 on end
 		device ref pch_espi on
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 0dd1456d42..eb7be69ca1 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -40,49 +40,58 @@ chip soc/intel/alderlake
 	register "PrmrrSize" = "0"
 
 	# Enable PCH PCIE RP 5 using CLK 2
-	register "PchPcieRpEnable[4]" = "1"
-	register "PcieClkSrcClkReq[2]" = "2"
-	register "PcieClkSrcUsage[2]" = "0x4"
-	register "PcieRpClkReqDetect[4]" = "1"
+	register "pch_pcie_rp[PCH_RP(5)]" = "{
+		.clk_src = 2,
+		.clk_req = 2,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
 
 	# Enable PCH PCIE RP 6 using CLK 5
-	register "PchPcieRpEnable[5]" = "1"
-	register "PcieClkSrcClkReq[5]" = "5"
-	register "PcieClkSrcUsage[5]" = "0x5"
-	register "PcieRpClkReqDetect[5]" = "1"
+	register "pch_pcie_rp[PCH_RP(6)]" = "{
+		.clk_src = 5,
+		.clk_req = 5,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
 
-	# Enable PCH PCIE RP 8 using CLK 6
-	register "PchPcieRpEnable[7]" = "1"
-	register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK
+	# Enable PCH PCIE RP 8 using free running CLK (0x80)
+	# Clock source is shared with LAN and hence marked as free running.
+	register "pch_pcie_rp[PCH_RP(8)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+	register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
 
 	# Enable PCH PCIE RP 9 using CLK 1
-	register "PchPcieRpEnable[8]" = "1"
-	register "PcieClkSrcClkReq[1]" = "1"
-	register "PcieClkSrcUsage[1]" = "0x8"
-	register "PcieRpClkReqDetect[8]" = "1"
+	register "pch_pcie_rp[PCH_RP(9)]" = "{
+		.clk_src = 1,
+		.clk_req = 1,
+		.flags = PCIE_RP_CLK_REQ_DETECT,
+	}"
 
 	# Enable PCH PCIE RP 11 for optane
-	register "PchPcieRpEnable[10]" = "1"
+	register "pch_pcie_rp[PCH_RP(11)]" = "{
+		.flags = PCIE_RP_CLK_SRC_UNUSED,
+	}"
+
 	# Hybrid storage mode
 	register "HybridStorageMode" = "1"
 
 	# Enable CPU PCIE RP 1 using CLK 0
-	register "CpuPcieRpEnable[0]" = "1"
-	register "PcieClkSrcUsage[0]" = "0x40"
+	register "cpu_pcie_rp[CPU_RP(1)]" = "{
+		.clk_req = 0,
+		.clk_src = 0,
+	}"
 
 	# Enable CPU PCIE RP 2 using CLK 3
-	register "CpuPcieRpEnable[1]" = "1"
-	register "PcieClkSrcUsage[3]" = "0x41"
+	register "cpu_pcie_rp[CPU_RP(2)]" = "{
+		.clk_req = 3,
+		.clk_src = 3,
+        }"
 
 	# Enable CPU PCIE RP 3 using CLK 4
-	register "CpuPcieRpEnable[2]" = "1"
-	register "PcieClkSrcUsage[4]" = "0x42"
-
-	# W/A to FSP issue where FSP is using PCH PCIE port
-	# enable UPD to download FW on CPU PCIE
-	register "PchPcieRpEnable[0]" = "1"
-	register "PchPcieRpEnable[2]" = "1"
-	register "PchPcieRpEnable[3]" = "1"
+	register "cpu_pcie_rp[CPU_RP(3)]" = "{
+		.clk_req = 4,
+		.clk_src = 4,
+	}"
 
 	register "SataSalpSupport" = "1"