diff options
| author | Youness Alaoui <youness.alaoui@puri.sm> | 2018-02-09 18:44:45 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-06 06:41:38 +0000 |
| commit | 0601f1e164a95342a7c381603284c11a9a588804 (patch) | |
| tree | d3caee1278c4acc12ccffc537125692e77a3c991 /src/mainboard | |
| parent | 59d89a8e599eb15582fbf56a11f08da08ff19ed3 (diff) | |
purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree
Although VmxEnable is currently ignored by FSP, a forthcoming patch
explicitly enables it in coreboot, so set it in anticipation of that.
Enable Intel SpeedStep to ensure the ACPI tables are generated for
the C-states/P-states which are required for the xen-acpi-processor
module to be loaded. Without it, the Qubes 4.0-rc4 installer will
complain at boot about modules that could not be loaded.
Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index b85ac3e034..84932b2024 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + register "eist_enable" = "1" + register "VmxEnable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index d240f023da..989c4ff485 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + register "eist_enable" = "1" + register "VmxEnable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE |