diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2004-03-25 17:50:06 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-03-25 17:50:06 +0000 |
| commit | edeff59c72f5ae0218a8366d38274947d2b48f8d (patch) | |
| tree | b8233902246110a7c494db7e700bf41bf136f129 /src/mainboard | |
| parent | 30667d75a63495e98fc5e228af510f29a6e575fe (diff) | |
YhLu's patch for multi-ht-chain for S2885
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/tyan/s2885/auto.c | 23 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2885/resourcemap.c | 6 |
2 files changed, 26 insertions, 3 deletions
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c index 307331375c..163491fb24 100644 --- a/src/mainboard/tyan/s2885/auto.c +++ b/src/mainboard/tyan/s2885/auto.c @@ -149,6 +149,22 @@ static void main(void) }, #endif }; + + static const struct ht_chain ht_c[] = { + { + .udev = PCI_DEV(0, 0x18, 0), + .upos = 0xc0, + .devreg = 0xe2, + .mindev = 1, + }, + { + .udev = PCI_DEV(0, 0x18, 0), + .upos = 0x80, + .devreg = 0xe6, + .mindev = 5, + + }, + }; int needs_reset; enable_lapic(); init_timer(); @@ -164,11 +180,16 @@ static void main(void) console_init(); setup_s2885_resource_map(); needs_reset = setup_coherent_ht_domain(); - needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); +// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); + needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); if (needs_reset) { print_info("ht reset -"); soft_reset(); } +#if 0 + dump_pci_devices(); +#endif + #if 0 print_pci_devices(); diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c index f2535bf02f..fcf99d87bd 100644 --- a/src/mainboard/tyan/s2885/resourcemap.c +++ b/src/mainboard/tyan/s2885/resourcemap.c @@ -252,8 +252,10 @@ static void setup_s2885_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007, +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203, +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003, // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x00000203, // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, |